whitequark 4b3a068b15 hdl.mem: use 1 as reset value for ReadPort.en. ... This is necessary for consistency, since for transparent read ports, we currently do not support .en at all (it is fixed at 1) due to YosysHQ/yosys#760. Before this commit, changing port transparency would require adding or removing an assignment to .en, which is confusing and error-prone. Also, most read ports are always enabled, so this behavior is also convenient.		2019-09-20 19:51:13 +00:00
..
__init__.py	hdl.xfrm: CEInserter→EnableInserter.	2019-08-12 13:39:26 +00:00
ast.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
ir.py	build.plat, hdl.ir: coordinate missing domain creation.	2019-08-19 22:52:01 +00:00
mem.py	hdl.mem: use 1 as reset value for ReadPort.en.	2019-09-20 19:51:13 +00:00
rec.py	hdl.rec: respect modifications to signals in Record.like().	2019-07-08 10:59:15 +00:00
xfrm.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00