whitequark f9b9c17a16 lib.fifo: work around Yosys issue with handling of \TRANSPARENT. ... Because of YosysHQ/yosys#1390, using a transparent port in AsyncFIFO, instead of being a no-op (as the semantics of \TRANSPARENT would require it to be in this case), results in a failure to infer BRAM. This can be easily avoided by using a non-transparent port instead, which produces the desirable result with Yosys. It does not affect the semantics on Xilinx platforms, since the interaction between the two ports in case of address collision is undefined in either transparent (WRITE_FIRST) or non-transparent (READ_FIRST) case, and the data out of the write port is not used at all. Fixes #172.		2019-09-20 19:54:27 +00:00
..
back	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
build	build.plat: bypass tool detection if NMIGEN_*_env is set.	2019-09-12 21:56:48 +00:00
compat	lib.cdc: make domain properties private.	2019-09-12 13:54:48 +00:00
hdl	hdl.mem: use 1 as reset value for ReadPort.en.	2019-09-20 19:51:13 +00:00
lib	lib.fifo: work around Yosys issue with handling of \TRANSPARENT.	2019-09-20 19:54:27 +00:00
test	hdl.mem: use 1 as reset value for ReadPort.en.	2019-09-20 19:51:13 +00:00
vendor	vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.	2019-09-20 16:26:27 +00:00
__init__.py	Remove nmigen.lib from prelude.	2019-09-06 06:53:06 +00:00
_toolchain.py	_toolchain,build.plat,vendor.*: add required_tools list and checks.	2019-08-31 00:05:47 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00