William D. Jones
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2412650f56
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hdl.dsl: Support Assert and Assume where an Assign can occur.
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2019-01-02 11:17:39 +00:00 |
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whitequark
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3c07d8d52c
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hdl.rec: include record name in error message.
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2019-01-01 03:39:12 +00:00 |
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whitequark
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031a9e2616
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hdl.rec: use a helpful error on unknown field reference.
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2019-01-01 03:35:34 +00:00 |
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whitequark
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d78e6c155b
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hdl.mem: add DummyPort, for testing and verification.
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2019-01-01 03:08:10 +00:00 |
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whitequark
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39eb2e8fa7
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lib.cdc: fix tests to actually run.
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2018-12-29 15:02:44 +00:00 |
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whitequark
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849c649259
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back.pysim: warn if simulation is not run.
This would have prevented 3ea35b85.
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2018-12-29 15:02:04 +00:00 |
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whitequark
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92a96e1644
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hdl.rec: add basic record support.
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2018-12-28 13:22:10 +00:00 |
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whitequark
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3ea35b8566
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lib.coding: fix tests to actually run, and fix code to fix tests.
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2018-12-27 21:45:55 +00:00 |
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whitequark
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470d66934f
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hdl.dsl: add support for fsm.ongoing().
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2018-12-27 16:19:01 +00:00 |
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whitequark
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528747703d
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lib.coding: port from Migen.
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2018-12-26 13:19:34 +00:00 |
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whitequark
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fe8cb55204
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lib.cdc: add tests for MultiReg.
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2018-12-26 12:58:30 +00:00 |
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whitequark
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35a44f017f
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hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
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2018-12-26 12:42:43 +00:00 |
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whitequark
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934546e633
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hdl.dsl: provide generated values for FSMs.
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2018-12-26 12:39:05 +00:00 |
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whitequark
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040811c2e5
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hdl.ir: add an API for retrieving generated values, like FSM signal.
This is useful for tests.
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2018-12-26 12:35:35 +00:00 |
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whitequark
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54e3195dcb
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hdl.dsl: implement FSM.
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2018-12-26 08:55:04 +00:00 |
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whitequark
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98f554aa08
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hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
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2018-12-24 02:17:28 +00:00 |
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whitequark
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1c7c75a254
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hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
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2018-12-24 02:02:59 +00:00 |
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whitequark
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621dddebfd
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hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
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2018-12-22 22:19:14 +00:00 |
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whitequark
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68dae9f50e
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hdl.ir: flatten hierarchy based on memory accesses, too.
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2018-12-22 21:43:46 +00:00 |
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whitequark
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ae0cb48fbb
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hdl.xfrm: implement LHSGroupAnalyzer.
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2018-12-22 06:58:24 +00:00 |
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whitequark
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f6772759c8
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hdl.ir: fix port propagation between siblings, in the other direction.
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2018-12-22 00:31:31 +00:00 |
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whitequark
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913339c04a
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hdl.ir: fix port propagation between siblings.
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2018-12-21 23:53:18 +00:00 |
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whitequark
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fa2af27bb0
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hdl.mem: ensure transparent read port model has correct latency.
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2018-12-21 13:01:08 +00:00 |
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whitequark
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48d13e47ec
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back.pysim: handle out of bounds ArrayProxy indexes.
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2018-12-21 12:32:08 +00:00 |
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whitequark
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e58d9ec74d
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hdl.mem: add simulation model for memory.
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2018-12-21 11:54:32 +00:00 |
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whitequark
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c49211c76a
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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whitequark
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b0bd7bfaca
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hdl.ir: correctly handle named output and inout ports.
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2018-12-21 04:03:03 +00:00 |
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whitequark
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f7fec804ec
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ir: allow non-Signals in Instance ports.
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2018-12-20 23:40:40 +00:00 |
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whitequark
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dbbcc49a71
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hdl.ast: Cat.{operands→parts}
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2018-12-18 19:15:50 +00:00 |
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whitequark
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4199674edd
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back.pysim: implement *.
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2018-12-18 18:02:21 +00:00 |
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whitequark
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07e9cfa939
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test.sim: add tests for sync functionality and errors.
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2018-12-18 17:53:50 +00:00 |
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whitequark
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c7f9386eab
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fhdl.ir: add black-box fragments, fragment parameters, and Instance.
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2018-12-17 22:55:39 +00:00 |
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whitequark
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8d1639a5a8
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hdl, back: add and use SignalSet/SignalDict.
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2018-12-17 17:21:29 +00:00 |
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whitequark
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015998eba9
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hdl.dsl: add clock domain support.
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2018-12-16 23:51:24 +00:00 |
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whitequark
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d4e8d3e95a
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back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
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2018-12-16 10:31:42 +00:00 |
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whitequark
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d9579219ee
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test.sim: generalize assertOperator. NFC.
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2018-12-15 21:08:29 +00:00 |
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whitequark
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20a04bca88
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back.pysim: implement Part.
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2018-12-15 20:58:06 +00:00 |
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whitequark
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54fb999c99
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back.pysim: implement ArrayProxy.
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2018-12-15 19:37:36 +00:00 |
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whitequark
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80c5343600
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hdl.ast: implement Array and ArrayProxy.
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2018-12-15 17:16:31 +00:00 |
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whitequark
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c6e7a93717
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hdl: appropriately rename tests. NFC.
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2018-12-15 16:13:53 +00:00 |
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whitequark
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790eb05a92
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Rename fhdl→hdl, genlib→lib.
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2018-12-15 14:25:31 +00:00 |
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whitequark
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b70340c0da
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pyback.sim: test Slice, Cat, Repl.
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2018-12-15 10:09:14 +00:00 |
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whitequark
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db4600d52b
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fhdl.ast, back.pysim: implement shifts.
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2018-12-15 09:58:30 +00:00 |
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whitequark
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46f5addf05
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fhdl.ast: refactor Operator.shape(). NFC.
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2018-12-15 09:46:20 +00:00 |
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whitequark
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f9f7921959
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fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
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2018-12-15 09:26:36 +00:00 |
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whitequark
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f5e8c9033d
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fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
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2018-12-15 09:26:23 +00:00 |
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whitequark
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2001359b66
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fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
Fixes #5.
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2018-12-14 22:48:17 +00:00 |
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whitequark
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579feaba4e
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fhdl.ir: Fragment.{drive→add_driver}
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2018-12-14 20:58:29 +00:00 |
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whitequark
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50ba443f92
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fhdl.ast: fix Switch with constant test.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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9307a31678
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back.pysim: Simulator({gtkw_signals→traces}=).
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2018-12-14 15:23:22 +00:00 |
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