whitequark
38b3c4af31
hdl.ast: implement shape for modulo operator.
2019-01-19 09:27:56 +00:00
whitequark
5e2b46f727
hdl.ast: add Value.implies.
2019-01-19 08:56:44 +00:00
whitequark
c5d67b0461
hdl.xfrm: mark internal registers used in lowering Sample().
2019-01-19 07:27:32 +00:00
whitequark
94b23dd2c8
doc: update COMPAT_SUMMARY.
2019-01-19 02:20:40 +00:00
whitequark
e3b5b2acc8
fhdl.specials: add compatibility shim for Tristate.
2019-01-19 02:20:40 +00:00
whitequark
3ed519383c
lib.fifo: fix simulation read/write methods to take only one cycle.
2019-01-19 01:38:09 +00:00
whitequark
45088f7824
compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered.
2019-01-19 01:06:51 +00:00
whitequark
97b990272e
lib.fifo: formally verify FIFO contract.
2019-01-19 00:52:56 +00:00
whitequark
b50b47d984
hdl.ast: give Assert and Assume their own src_loc.
...
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
2019-01-19 00:08:51 +00:00
whitequark
66466a8a0e
back.rtlil: only emit each AnyConst/AnySeq cell once.
...
These are semantically like signals, not like constants.
2019-01-18 01:34:48 +00:00
Alain Péteut
60089db075
cli: add missing default for generate
2019-01-17 20:45:07 +00:00
whitequark
5a831ce31c
lib.fifo: add basic formal specification.
2019-01-17 05:40:25 +00:00
whitequark
fa8e876356
hdl.ast: allow sampling ClockSignal, ResetSignal.
2019-01-17 05:23:06 +00:00
whitequark
8c96675580
hdl.ast: add Past, Stable, Rose, Fell.
2019-01-17 04:31:27 +00:00
whitequark
16f90d3585
formal: extract from toplevel module.
...
The nMigen formal language is about to get *much* larger and will
keep growing faster than the rest of nMigen language, so it makes
good sense to extract it. Further, this makes it easier to qualify
formal keywords like `formal.AnyConst()` without directly importing
hdl.ast.
2019-01-17 01:43:07 +00:00
whitequark
198efcad31
hdl.xfrm: add SampleLowerer.
2019-01-17 01:41:02 +00:00
whitequark
b3de114d67
hdl.ast: add Sample.
2019-01-17 01:36:27 +00:00
whitequark
b78a2be9f6
lib.fifo: port sync FIFO queues from Migen.
2019-01-16 17:20:38 +00:00
whitequark
cb2f18ee37
hdl.ast: fix naming of Signal.like() signals when tracer fails.
2019-01-16 17:20:38 +00:00
whitequark
f2425001aa
back.rtlil: slightly nicer naming for $next signals. NFC.
2019-01-16 17:20:38 +00:00
whitequark
935bf2d8cf
back.rtlil: rename \sig$next to $next$sig.
...
These used to serve a useful purpose being public, back when the RTLIL
backend was immature. Not anymore; now they merely clutter up views
in gtkwave and so on.
2019-01-16 14:51:20 +00:00
whitequark
bfe246a127
Travis: install SymbiYosys and Yices2.
...
In preparation for adding formal tests.
2019-01-16 01:06:51 +00:00
whitequark
6191760c30
Unbreak 655d02d5.
2019-01-15 23:09:10 +00:00
William D. Jones
655d02d5b8
back.rtlil: Generate $anyconst and $anyseq cells.
2019-01-15 22:52:45 +00:00
William D. Jones
77728c2dea
hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.
2019-01-15 22:52:45 +00:00
William D. Jones
6fdbc3d885
hdl.ast: Add AnyConst and AnySeq value types.
2019-01-15 22:52:45 +00:00
Sebastien Bourdeauducq
1880686e2e
README: add LambdaConcept sponsorship
2019-01-15 15:58:38 +08:00
whitequark
c4276f7cf7
lib.io: pass pin to platform.get_tristate().
2019-01-14 21:39:19 +00:00
whitequark
b534e92dd5
hdl.ir: allow explicitly requesting flattening.
2019-01-14 17:04:23 +00:00
whitequark
6f66885c09
lib.io: lower to platform-independent tristate buffer.
2019-01-14 16:50:04 +00:00
whitequark
011bf2258e
hdl: make ClockSignal and ResetSignal usable on LHS.
...
Fixes #8 .
2019-01-14 15:38:16 +00:00
whitequark
664b4bcb3a
hdl.dsl: cases wider than switch test value are unreachable.
...
In 3083c1d6
2019-01-13 08:51:49 +00:00
whitequark
3083c1d6dd
hdl.dsl: accept (but warn on) cases wider than switch test value.
...
Fixes #13 .
2019-01-13 08:46:28 +00:00
whitequark
cbf7bd6e31
back.pysim: handle non-driven, non-port signals.
...
Fixes #20 .
2019-01-13 08:31:38 +00:00
whitequark
06faeee357
back.verilog: better error message if Yosys is not found.
...
Fixes #17 .
2019-01-13 08:10:23 +00:00
whitequark
307de722cb
back.verilog: remove undriven check.
...
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.
Fixes #23 .
2019-01-08 22:43:09 +00:00
Adam Greig
560bb007cc
Give the top level scope a name to fix VCD hierarchy.
2019-01-06 00:10:37 +00:00
whitequark
a2b04d71d0
hdl.ast: allow slicing [n:n] into n-bit value.
2019-01-02 18:14:57 +00:00
whitequark
ef1e0b8d55
back.rtlil: translate empty slices correctly.
2019-01-02 18:14:29 +00:00
William D. Jones
f31055a4ef
back.rtlil: Generate RTLIL for Assert/Assume statements.
2019-01-02 11:17:39 +00:00
William D. Jones
f77dc40256
hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.
2019-01-02 11:17:39 +00:00
William D. Jones
2412650f56
hdl.dsl: Support Assert and Assume where an Assign can occur.
2019-01-02 11:17:39 +00:00
William D. Jones
e6517a33c7
hdl.ast: Add Assert and Assign statements.
2019-01-02 11:17:39 +00:00
whitequark
ea7e19ed5c
hdl.ast: experimentally add Value._as_const.
...
Useful for writing e.g. decoders that accept Cat, etc as argument.
2019-01-01 09:50:39 +00:00
whitequark
1a9dcd2f28
back.rtlil: fix typo.
2019-01-01 08:50:28 +00:00
whitequark
3c07d8d52c
hdl.rec: include record name in error message.
2019-01-01 03:39:12 +00:00
whitequark
031a9e2616
hdl.rec: use a helpful error on unknown field reference.
2019-01-01 03:35:34 +00:00
whitequark
d78e6c155b
hdl.mem: add DummyPort, for testing and verification.
2019-01-01 03:08:10 +00:00
whitequark
ae3c5834ed
back.rtlil: match shape of Array elements to ArrayProxy shape.
...
Fixes #15 .
2018-12-31 03:43:34 +00:00
whitequark
cdc40eaa9b
back.rtlil: fix typo.
2018-12-31 03:37:38 +00:00
