Commit graph

1559 commits

Author SHA1 Message Date
Wanda 6d65dc1366 hdl, back.rtlil: track and emit module/submodule locations. 2024-02-19 21:41:32 +00:00
Wanda 188eb8d453 back.rtlil: emit wire signedness according to Signal signedness. 2024-02-16 22:03:30 +00:00
Wanda 6058ad35cf hdl._ast: make Shape immutable and hashable.
Fixes #1127.
2024-02-16 15:21:05 +00:00
Wanda 24a392887a Implement RFC 43: Rename reset= to init=. 2024-02-15 22:52:24 +00:00
Catherine b30c87fa3e pyproject: suppress superfluous warning. 2024-02-15 19:58:19 +00:00
Catherine 52842ee524 docs: fix link rot. 2024-02-15 19:58:19 +00:00
Wanda e3324e1456 hdl._dsl: fix using 0-width Switch with integer keys.
Fixes #1133.
2024-02-14 19:13:14 +00:00
Wanda 5ffb48b5fb hdl._ast: fix using 0-width Switch with integer keys.
This comes up in `AssignmentLegalizer`-produced `Switch`es for
`ArrayProxy`.
2024-02-14 11:52:35 +00:00
Wanda 0ecd06a7e5 sim: fix using 0-width Switch. 2024-02-14 11:51:19 +00:00
Wanda 8033ddf05e pyproject: change yosys-yowasp requirement to match RTLIL backend. 2024-02-14 11:50:36 +00:00
Wanda 353a8ce7e3 README: add the full list of supported AMD devices. 2024-02-13 21:47:18 +00:00
Catherine 4a8dd808c3 Ensure we build sensible sdists. 2024-02-13 12:52:05 +00:00
Catherine 8677ced404 Update README. 2024-02-13 12:52:05 +00:00
Catherine 0eac9c3fd0 CI: verify package metadata on all builds. 2024-02-13 12:52:05 +00:00
Catherine 841ab94a76 CI: publish packages automatically. 2024-02-13 11:43:44 +00:00
Catherine b9c9948038 docs: use :py: role for inline Python code, not :pc:.
I originally picked :pc: as it is short for "python code", but it is
obscure and :py: is not taken, so a much more obvious role can be used
instead. Also, we all typo :pc: as :py: all the time anyway.
2024-02-13 10:38:36 +00:00
Catherine 3cb5f63aba _toolchain.yosys: add JavaScript (Pyodide) support.
In this environment it's not feasible, or at least it's not documented
how, to distribute JavaScript code by packaging it as a wheel; only
Wasm code (as shared objects) can be distributed this way. The current
`amaranth-yosys` strategy would not work even though wheels can be
installed on Pyodide, and Yosys will need to be explicitly provided by
the environment instead.

The implementation is sufficiently generic that non-Pyodide hosts could
potentially make use of it, though it doesn't seem like any exist at
the moment.
2024-02-13 07:31:53 +00:00
Catherine 9aebf49565 sim.pysim: only import pyvcd when needed.
In some environments (e.g. Pyodide) it may be advantageous to not load
this library, and with the import at file level, it makes the entire
simulator unusable, not just `PySimEngine.write_vcd`.

This might also help people whose Python environments are unusually
broken, whom we've historically accommodated.
2024-02-13 07:31:53 +00:00
Wanda 5797643c9c docs: remove leftover TODO and warning from #1003, fix matches docs. 2024-02-13 06:23:23 +00:00
Wanda a0c8b18546 vendor._intel: use dff instead of $dff.
Fixes #1046.
2024-02-13 06:14:59 +00:00
Catherine 3867623727 docs/reference: describe out-of-bounds behavior of bit_select/word_select. 2024-02-13 05:44:52 +00:00
Catherine 2dea83cffd docs/reference: minor fixes. 2024-02-13 05:44:52 +00:00
Wanda 1dc1d2d709 vendor.lattice_ice40: use SB_DFF instead of $dff. 2024-02-13 05:42:31 +00:00
Catherine eebb6ec3bb back.verilog: require Yosys 0.38.
This avoids the awkward requirement due to the bug in Yosys 0.37, and
will soon be required anyway once the `$check` cell is emitted.
2024-02-13 05:27:23 +00:00
Wanda 0da439cce1 hdl._ast: deprecate ValueCastable.lowermethod. 2024-02-13 05:06:06 +00:00
Wanda e2fd819742 hdl._ast: fix shift_right and as_signed edge cases. 2024-02-13 04:52:38 +00:00
Catherine 0056e982c5 docs/reference: document Value, ValueCastable, ValueLike.
Co-authored-by: Wanda <wanda@phinode.net>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-02-13 03:22:04 +00:00
Wanda 4a3a9a90e8 hdl._nir: implement __repr__ on NIR classes. 2024-02-13 01:12:44 +00:00
Wanda 4014f6429c Implement RFC 27 amendment: deprecate add_sync_process, not add_process. 2024-02-12 18:26:48 +00:00
Wanda 2d42d649ee tests: stop using implicit ports. 2024-02-12 13:24:54 +00:00
Wanda 18e5bcd6f7 hdl._nir: fix docstring typos. 2024-02-11 16:34:12 +00:00
Catherine 84709e2f00 hdl: remove ValueKey, ValueDict, ValueSet.
These aren't used internally anymore and haven't been used in any code
published on GitHub, so they are simply removed rather than deprecated.
2024-02-11 13:50:06 +00:00
Catherine 6f44438e58 hdl._ir,hdl._nir,back.rtlil: new intermediate representation.
The new intermediate representation will enable global analyses
on Amaranth code without lowering it to another representation
such as RTLIL.

This commit also changes the RTLIL builder to use the new IR.

Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Catherine 78981232d9 hdl.xfrm: add assignment legalizer.
Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Catherine 10117607a3 build.plat: fix toolchain environment variable check, #2.
Fixes typo introduced in commit 78b90fba.
2024-02-11 08:21:06 +00:00
Wanda 05ac36751a sim: prefix fields with \.
Fixes #1001.
2024-02-09 21:15:34 +00:00
Wanda 45dbce13df hdl: consistently use "comb" for combinatorial domain.
Fixes #1097.
2024-02-09 19:32:55 +00:00
Wanda b6c5294e50 hdl.MemoryInstance: refactor and add first-class simulation support. 2024-02-09 17:36:15 +00:00
Wanda f4daf74634 sim: Add tests for memory access. 2024-02-09 17:36:15 +00:00
Catherine 83a9149c4c CI: Update actions to Node 20. 2024-02-09 13:53:46 +00:00
Wanda 6e06fc013f hdl.ir: associate statements with domains.
Fixes #1079.
2024-02-09 05:33:16 +00:00
Wanda 09854fa775 hdl.ast: make it impossible to construct *Castable instances.
Fixes #1072.
2024-02-09 05:26:58 +00:00
Catherine ace7aea375 lib.wiring: track member source locations.
The source location is set to the place where `In`/`Out` was created.

The source location of the instantiation is tracked but overwritten;
we will need to change the internal structure storing those to be able
to include both.

Fixes #1085.
2024-02-08 16:04:44 +00:00
Catherine 78b90fbafa build.plat,vendor: fix toolchain environment variable check.
The bug was introduced in commit 15b6068c. A changelog entry was also
missing.

Fixes #1089.
2024-02-08 11:37:59 +00:00
Daniel Estévez d8f70be4d9 xilinx: use FDPE instances to implement get_async_ff_sync()
This closes #721 by implementing get_async_ff_sync() using FDPE
primitives to obtain exactly the netlist that we want. This consits
of a chain of N FPDEs (by default N = 2) with all their PRE pins
connected to the reset for a positive edge reset or to the ~reset
for a negative edge reset. The D pin of the first FDPE in the chain
is connected to GND.

To make timing analysis work correctly, two new attributes are
introduced: amaranth.vivado.false_path_pre and
amaranth.vivado.max_delay_pre. These work similarly to
amaranth.vivado.false_path and amaranth.vivado.max_delay, but affect
only the PRE pin, which is what is needed for this synchronizer.
The TCL has been modified to generate constraints using these
attributes, and there are comments explaining how to use the attributes
directly in an XDC file in case the user wants to manage their XDC
file manually instead of using the TCL.
2024-02-08 11:30:51 +00:00
Catherine 9e75962c35 Implement RFC 27: Testbench processes for the simulator.
Co-authored-by: Wanda <wanda@phinode.net>
2024-02-06 23:12:07 +00:00
Wanda f48b8650c4 sim: fix simulation loop when process catches an injected exception. 2024-02-06 18:55:11 +00:00
Catherine 15b6068c57 Remove features deprecated in past releases. 2024-02-06 15:55:05 +00:00
Vegard Storheil Eriksen 5e2f3b7992 Implement RFC 42: Const from shape-castable. 2024-02-06 10:18:12 +00:00
Wanda 089213e19f Implement RFC 46: Change Shape.cast(range(1)) to unsigned(0). 2024-02-06 10:05:10 +00:00