whitequark
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9ba2efd86b
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build.{res,plat}: use xdr=0 as default, not xdr=1.
The previous behavior was semantically incorrect.
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2019-06-03 03:36:32 +00:00 |
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whitequark
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3327deae92
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vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.
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2019-06-03 03:01:56 +00:00 |
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whitequark
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dc17d06fe9
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vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
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2019-06-03 02:51:59 +00:00 |
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whitequark
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e4ebe03115
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vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles.
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2019-06-02 04:12:50 +00:00 |
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Simon Kirkby
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358b98e5de
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vendor.tinyfpga_b: implement.
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2019-06-02 01:20:09 +00:00 |
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whitequark
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321d245e95
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vendor.fpga.lattice_ice40: implement.
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2019-06-01 16:47:01 +00:00 |
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