whitequark
|
eeb023a7f5
|
compat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=.
|
2019-01-22 06:56:46 +00:00 |
|
|
whitequark
|
52a9f818f1
|
compat.genlib.cdc: add missing import.
|
2019-01-20 03:03:56 +00:00 |
|
|
whitequark
|
c110fe6a9d
|
compat.genlib.cdc: add GrayCounter and GrayDecoder shims.
|
2019-01-20 02:29:08 +00:00 |
|
|
whitequark
|
e3b5b2acc8
|
fhdl.specials: add compatibility shim for Tristate.
|
2019-01-19 02:20:40 +00:00 |
|
|
whitequark
|
45088f7824
|
compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered.
|
2019-01-19 01:06:51 +00:00 |
|
|
Jean-François Nguyen
|
73ed870309
|
compat.genlib.coding: fix import.
|
2018-12-26 14:30:01 +00:00 |
|
|
whitequark
|
528747703d
|
lib.coding: port from Migen.
|
2018-12-26 13:19:34 +00:00 |
|
|
whitequark
|
3448953f61
|
compat.genlib.fsm: fix naming for non-Signal LHS.
|
2018-12-22 22:00:58 +00:00 |
|
|
whitequark
|
99b778158d
|
compat: use nicer names for next_value/next_value_ce signals.
|
2018-12-22 02:05:49 +00:00 |
|
|
whitequark
|
5361b4c22b
|
compat: fix confusing naming for memory port address signal.
|
2018-12-22 00:53:05 +00:00 |
|
|
whitequark
|
0df543b204
|
compat: do not finalize native submodules twice.
|
2018-12-22 00:02:31 +00:00 |
|
|
whitequark
|
00ef7a78d3
|
compat: provide verilog.convert shim.
|
2018-12-21 13:53:06 +00:00 |
|
|
whitequark
|
568d3c5b7d
|
compat: provide Memory shim.
|
2018-12-21 13:15:52 +00:00 |
|
|
whitequark
|
0f2c7e7161
|
compat: import genlib.record from Migen.
|
2018-12-18 20:04:22 +00:00 |
|
|
whitequark
|
a90748303c
|
compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
|
2018-12-18 20:03:32 +00:00 |
|
|
whitequark
|
015998eba9
|
hdl.dsl: add clock domain support.
|
2018-12-16 23:51:24 +00:00 |
|
|
whitequark
|
db5fd1e4c4
|
compat.fhdl.structure: only convert to bool in If/Elif if necessary.
|
2018-12-16 17:41:42 +00:00 |
|
|
whitequark
|
286a8009c8
|
compat.fhdl: reexport Array.
|
2018-12-16 10:39:54 +00:00 |
|
|
whitequark
|
790eb05a92
|
Rename fhdl→hdl, genlib→lib.
|
2018-12-15 14:25:31 +00:00 |
|
|
whitequark
|
9010805040
|
compat.fhdl.structure: handle If/Elif with multi-bit condition.
|
2018-12-15 00:10:54 +00:00 |
|
|
whitequark
|
ecea721f43
|
compat.fhdl.module: allow adding native submodules to compat modules.
|
2018-12-14 23:56:50 +00:00 |
|
|
whitequark
|
1c7b43ea49
|
Fix deprecations in Python 3.7.
|
2018-12-14 23:56:50 +00:00 |
|
|
whitequark
|
e230383aac
|
back.pysim: make initial phase configurable.
|
2018-12-14 16:46:16 +00:00 |
|
|
whitequark
|
0ef5ced492
|
compat.sim: match clock period.
|
2018-12-14 16:39:52 +00:00 |
|
|
whitequark
|
17d26c8329
|
compat: add run_simulation shim.
|
2018-12-14 16:22:18 +00:00 |
|
|
whitequark
|
3bc3647380
|
compat.fhdl.module: fix specials.
|
2018-12-14 16:14:08 +00:00 |
|
|
whitequark
|
3b23645fb7
|
compat: add fhdl.specials.TSTriple shim.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
a0d555a9fc
|
compat: add genlib.cdc.MultiReg shim.
|
2018-12-14 16:01:38 +00:00 |
|
|
whitequark
|
baba47251c
|
compat.fhdl.module: update deprecation messages.
|
2018-12-14 16:01:38 +00:00 |
|
|
whitequark
|
b58715c5dc
|
ast, back.pysim: allow specifying user-defined decoders for signals.
|
2018-12-14 09:02:29 +00:00 |
|
|
whitequark
|
6251c95d4e
|
compat.genlib.fsm: import/wrap Migen code.
|
2018-12-13 12:41:19 +00:00 |
|
|
whitequark
|
f4340c19bb
|
fhdl: cd_name→domain.
|
2018-12-13 10:15:01 +00:00 |
|
|
whitequark
|
22c76e5f90
|
compat.fhdl.module: implement finalization.
|
2018-12-13 02:36:15 +00:00 |
|
|
whitequark
|
f0f4c0ce61
|
fhdl.ast: bits_sign→shape.
|
2018-12-13 02:06:58 +00:00 |
|
|
whitequark
|
b4dab74b2e
|
compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
|
2018-12-12 15:47:34 +00:00 |
|
|
whitequark
|
356852a570
|
compat.fhdl.bitcontainer: import/wrap Migen code.
|
2018-12-12 15:22:34 +00:00 |
|