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Author SHA1 Message Date
whitequark 2d2ab6e09d lib.cdc: make domain properties private. 
It is not correct to access domain properties from user code, because
it will not match the reality if DomainRenamer has been applied to
the module.
 2019-09-12 13:54:48 +00:00
whitequark 9893e3c044 lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions. 
Refs #97.
 2019-09-12 13:48:45 +00:00
whitequark 8f659b6cd6 lib.cdc: adjust MultiReg for new CDC primitive conventions. 
Refs #97.
 2019-09-12 13:48:24 +00:00
whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). 
Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
 2019-08-19 19:49:51 +00:00
whitequark 84f2c3df2b compat.fhdl.decorators: avoid using deprecated NativeCEInserter. 2019-08-18 16:27:11 +00:00
whitequark e6b1e3de1a compat.fhdl.decorators: port from oMigen. 2019-08-08 08:09:28 +00:00
whitequark 5c626e33bf compat.fhdl.module: fix finalization of transformed compat submodules. 
Before this commit, the TransformedElaboratable of a CompatModule
would be ignored, and .get_fragment() would be used to retrieve
the CompatModule within.

After this commit, the finalization process is reworked to match
oMigen's finalization closely, and all submodules, native and compat,
are added in the same way that preserves applied transforms.
 2019-08-08 07:45:34 +00:00
whitequark 0fe05188e8 compat.fhdl.specials: track changes in build.plat. 2019-08-03 22:52:34 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark 447bfa6ad5 compat.genlib.fsm: fix after commit dac62754. 2019-07-08 10:12:26 +00:00
whitequark 668ff40a75 compat.fhdl.specials: mark CompatMemory as Elaboratable. 
This suppresses a warning that is not useful in the compat context.
 2019-07-03 13:28:57 +00:00
whitequark eeb6aca93d compat.fhdl.specials: use "sync" as default domain, not "sys". 
In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
 2019-07-03 13:25:12 +00:00
whitequark c98b8f7c07 compat.fhdl.specials: fix Memory.get_port() after 94e8f479. 
This also makes sure the native ports are instantiated for correct
clock domain.
 2019-07-03 13:24:00 +00:00
whitequark 9eb81609d6 compat.fhdl.structure: fix If/Elif/Else after 32446831. 2019-07-03 13:19:15 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark 2f7e52369c compat.fhdl.structure: fix typo. 2019-06-25 22:01:14 +00:00
whitequark b1af0601fa compat.fhdl.structure: simplify handling of default case. 2019-06-25 22:01:14 +00:00
whitequark 2566747061 compat.fhdl.structure: fix Case().makedefault(). 
Fixes #100.
 2019-06-13 03:56:57 +00:00
whitequark f689b777b4 compat.fhdl.structure: always order default case as the very last. 2019-06-13 03:56:57 +00:00
whitequark 537d91851d compat.fhdl.module: silence "unused elaboratable" warnings. 2019-06-04 13:09:36 +00:00
whitequark 38917e4523 compat.fhdl.specials: fix platform lowering for TSTriple again. 2019-06-04 13:03:56 +00:00
whitequark 79a3710255 compat.fhdl.specials: fix platform lowering. 
get_tristate only has O/OE; the triple is created by get_input_output.
 2019-06-04 12:26:09 +00:00
whitequark 0cbb743df9 compat.fhdl.module: implement some TODO'd deprecation warnings. 2019-06-04 12:00:02 +00:00
whitequark 39ca0e6fa6 compat.fhdl.module: CompatModule should be elaboratable. 
Fixes #83.
 2019-06-04 11:11:31 +00:00
whitequark 4c443a7ef5 compat.fhdl.specials: TSTriple is not an elaboratable. 2019-06-03 09:39:38 +00:00
Chris Osterwood 699fe5a675 Add import so that Tristate.elaborate builds 2019-05-20 16:34:31 +00:00
Alain Péteut c8e92c0612 compat.fhdl.specials: fix Tristate, TSTriple. 
* fix TSTriple instance.
* TSTriple, Tristate: tag as Elaboratable
 2019-04-22 09:57:12 +00:00
Alain Péteut 371dc8bebe compat.fhdl.specials: fix Tristate. 2019-04-22 08:49:08 +00:00
whitequark 93d15abcf1 compat.fhdl.specials: fix TSTriple. 2019-04-22 08:15:03 +00:00
whitequark 287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
whitequark e844b0e095 compat.fhdl.module: fix typo. 2019-01-26 23:08:55 +00:00
whitequark ce7ba70462 compat.fhdl.specials: fix __all__ list. 2019-01-26 22:59:33 +00:00
whitequark 6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer. 2019-01-26 18:24:36 +00:00
whitequark 2fb85a6170 compat.fifo: fix _FIFOInterface deprecation wrapper. 2019-01-26 18:23:58 +00:00
whitequark 4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
whitequark 7890c0adc8 test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00
whitequark 4887771e4a compat.sim: fix deprecated stdlib import. 2019-01-26 15:26:54 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 4922a73c5d test.compat: import tests from Migen as appropriate. 
test_signed and test_coding are adjusted slightly to account for
differences in comb propagation between the simulators; we might want
to revert that eventually.
 2019-01-26 01:01:03 +00:00
whitequark eeb023a7f5 compat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=. 2019-01-22 06:56:46 +00:00
whitequark 52a9f818f1 compat.genlib.cdc: add missing import. 2019-01-20 03:03:56 +00:00
whitequark c110fe6a9d compat.genlib.cdc: add GrayCounter and GrayDecoder shims. 2019-01-20 02:29:08 +00:00
whitequark e3b5b2acc8 fhdl.specials: add compatibility shim for Tristate. 2019-01-19 02:20:40 +00:00
whitequark 45088f7824 compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered. 2019-01-19 01:06:51 +00:00
Jean-François Nguyen 73ed870309 compat.genlib.coding: fix import. 2018-12-26 14:30:01 +00:00
whitequark 528747703d lib.coding: port from Migen. 2018-12-26 13:19:34 +00:00
whitequark 3448953f61 compat.genlib.fsm: fix naming for non-Signal LHS. 2018-12-22 22:00:58 +00:00
whitequark 99b778158d compat: use nicer names for next_value/next_value_ce signals. 2018-12-22 02:05:49 +00:00
whitequark 5361b4c22b compat: fix confusing naming for memory port address signal. 2018-12-22 00:53:05 +00:00
whitequark 0df543b204 compat: do not finalize native submodules twice. 2018-12-22 00:02:31 +00:00