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152 commits

Author SHA1 Message Date
whitequark
c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. 
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
 2019-06-03 02:39:14 +00:00
whitequark
b8a61edc2f hdl.dsl: allow adding submodules with computed name, like with domains. 2019-06-03 02:22:55 +00:00
whitequark
b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance. 
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
 2019-06-03 02:12:01 +00:00
whitequark
b0ba960296 hdl.ir: silence unused elaboratable warning on interpreter crash. 2019-05-26 10:48:39 +00:00
whitequark
2b7dc37ffe hdl.rec: allow providing fields during construction. 
This allows creating records populated with e.g. signals with custom
names, or sub-records that are instances of Record subclasses.
 2019-05-25 22:06:56 +00:00
whitequark
3392708e2b Consider Instances a part of containing fragment for use-def purposes. 
Fixes #70.
 2019-05-25 20:13:43 +00:00
whitequark
c337246fc5 hdl.ir: when adding sync domain to a design, also add it to ports. 
Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
 2019-05-15 06:44:50 +00:00
whitequark
39bc59c924 hdl.ir: during port propagation, defs should take priority over uses. 2019-05-13 15:34:13 +00:00
whitequark
744e33f42d hdl: make all public Value classes other than Record final. 
In some cases, nMigen uses type() instead of isinstance() to dispatch
on types. Make sure all such uses of type() are robust; in addition,
make it clear that nMigen AST classes are not meant to be subclassed.
(Record is an exception.)

Fixes #65.
 2019-05-12 05:40:17 +00:00
whitequark
958cb18b88 hdl.ir: only pull explicitly specified ports to toplevel, if any. 
Fixes #30.
 2019-05-12 05:21:23 +00:00
whitequark
585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark
44711b7d08 hdl.ir: detect elaboratables that are created but not used. 
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
 2019-04-21 08:52:57 +00:00
whitequark
33f9bd2a1d hdl.ast: accept Signals with identical min/max bounds. 
And produce a 0-bit signal.

Fixes #58.
 2019-04-21 07:16:59 +00:00
whitequark
ce1eff5464 hdl.rec: implement Record.connect. 
Fixes #31.
 2019-04-21 06:37:08 +00:00
whitequark
611c25f909 hdl.rec: fix slicing of records. 2019-04-19 19:55:39 +00:00
whitequark
dda8f34d39 hdl.xfrm: handle classes that inherit from Record. 2019-04-18 17:06:33 +00:00
whitequark
50fa2516fa hdl.ast: fix some type checks. 2019-04-10 04:33:44 +00:00
whitequark
0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. 
Fixes #29.
 2019-04-10 00:23:11 +00:00
whitequark
49eef77c53 hdl: remove deprecated get_fragment() and lower() methods. 2019-04-09 23:53:43 +00:00
whitequark
a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). 2019-04-03 14:59:01 +00:00
anuejn
3c95299c4e hdl.rec: separate record and signal name with __, not _. 
This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
 2019-03-25 14:26:00 +00:00
whitequark
81ee2db163 hdl.ast: fix typo. 
Fixes #49.
 2019-03-25 10:50:39 +00:00
whitequark
e93bf4bf4b tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00
whitequark
cac4b10b82 hdl.rec: remove __slots__. 
Left in by mistake.
 2019-03-03 18:21:22 +00:00
whitequark
8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark
bc5a127fd2 hdl.ast: fix ValueKey for Cat. 2019-01-26 23:25:34 +00:00
whitequark
4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark
f71e0fffbb hdl.ast: fix shape calculation for *. 
This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
 2019-01-26 00:56:40 +00:00
whitequark
38b3c4af31 hdl.ast: implement shape for modulo operator. 2019-01-19 09:27:56 +00:00
whitequark
5e2b46f727 hdl.ast: add Value.implies. 2019-01-19 08:56:44 +00:00
whitequark
c5d67b0461 hdl.xfrm: mark internal registers used in lowering Sample(). 2019-01-19 07:27:32 +00:00
whitequark
b50b47d984 hdl.ast: give Assert and Assume their own src_loc. 
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
 2019-01-19 00:08:51 +00:00
whitequark
66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. 
These are semantically like signals, not like constants.
 2019-01-18 01:34:48 +00:00
whitequark
fa8e876356 hdl.ast: allow sampling ClockSignal, ResetSignal. 2019-01-17 05:23:06 +00:00
whitequark
8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark
198efcad31 hdl.xfrm: add SampleLowerer. 2019-01-17 01:41:02 +00:00
whitequark
b3de114d67 hdl.ast: add Sample. 2019-01-17 01:36:27 +00:00
whitequark
cb2f18ee37 hdl.ast: fix naming of Signal.like() signals when tracer fails. 2019-01-16 17:20:38 +00:00
William D. Jones
77728c2dea hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children. 2019-01-15 22:52:45 +00:00
William D. Jones
6fdbc3d885 hdl.ast: Add AnyConst and AnySeq value types. 2019-01-15 22:52:45 +00:00
whitequark
b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark
011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. 
Fixes #8.
 2019-01-14 15:38:16 +00:00
whitequark
664b4bcb3a hdl.dsl: cases wider than switch test value are unreachable. 
In 3083c1d6 they were erroneously fixed via truncation.
 2019-01-13 08:51:49 +00:00
whitequark
3083c1d6dd hdl.dsl: accept (but warn on) cases wider than switch test value. 
Fixes #13.
 2019-01-13 08:46:28 +00:00
whitequark
a2b04d71d0 hdl.ast: allow slicing [n:n] into n-bit value. 2019-01-02 18:14:57 +00:00
William D. Jones
f77dc40256 hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children. 2019-01-02 11:17:39 +00:00
William D. Jones
2412650f56 hdl.dsl: Support Assert and Assume where an Assign can occur. 2019-01-02 11:17:39 +00:00
William D. Jones
e6517a33c7 hdl.ast: Add Assert and Assign statements. 2019-01-02 11:17:39 +00:00
whitequark
ea7e19ed5c hdl.ast: experimentally add Value._as_const. 
Useful for writing e.g. decoders that accept Cat, etc as argument.
 2019-01-01 09:50:39 +00:00
whitequark
3c07d8d52c hdl.rec: include record name in error message. 2019-01-01 03:39:12 +00:00