William D. Jones
e6517a33c7
hdl.ast: Add Assert and Assign statements.
2019-01-02 11:17:39 +00:00
whitequark
ea7e19ed5c
hdl.ast: experimentally add Value._as_const.
...
Useful for writing e.g. decoders that accept Cat, etc as argument.
2019-01-01 09:50:39 +00:00
whitequark
3c07d8d52c
hdl.rec: include record name in error message.
2019-01-01 03:39:12 +00:00
whitequark
031a9e2616
hdl.rec: use a helpful error on unknown field reference.
2019-01-01 03:35:34 +00:00
whitequark
d78e6c155b
hdl.mem: add DummyPort, for testing and verification.
2019-01-01 03:08:10 +00:00
whitequark
39eb2e8fa7
lib.cdc: fix tests to actually run.
2018-12-29 15:02:44 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
d66bbb0df8
tracer: factor out get_src_loc().
2018-12-28 01:31:24 +00:00
whitequark
470d66934f
hdl.dsl: add support for fsm.ongoing().
2018-12-27 16:19:01 +00:00
whitequark
de50ccec90
hdl.mem: add missing __all__.
2018-12-27 16:19:01 +00:00
whitequark
35a44f017f
hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
2018-12-26 12:42:43 +00:00
whitequark
934546e633
hdl.dsl: provide generated values for FSMs.
2018-12-26 12:39:05 +00:00
whitequark
040811c2e5
hdl.ir: add an API for retrieving generated values, like FSM signal.
...
This is useful for tests.
2018-12-26 12:35:35 +00:00
whitequark
597d778cf6
examples: add an FSM usage example (UART receiver).
2018-12-26 10:10:27 +00:00
whitequark
72039b6072
hdl.dsl: add signal decoder to FSM state signal.
2018-12-26 09:45:12 +00:00
whitequark
54e3195dcb
hdl.dsl: implement FSM.
2018-12-26 08:55:04 +00:00
whitequark
f05bd2a137
hdl.mem: allow omitting memory simulation logic.
...
Trying to transform very large arrays is slow.
2018-12-24 11:53:59 +00:00
whitequark
98f554aa08
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
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This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
2018-12-24 02:17:28 +00:00
whitequark
1c7c75a254
hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
2018-12-24 02:02:59 +00:00
whitequark
621dddebfd
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
2018-12-22 22:19:14 +00:00
whitequark
68dae9f50e
hdl.ir: flatten hierarchy based on memory accesses, too.
2018-12-22 21:43:46 +00:00
whitequark
fd89d2fc9d
hdl.ir: factor out _merge_subfragment. NFC.
2018-12-22 19:04:49 +00:00
whitequark
ae0cb48fbb
hdl.xfrm: implement LHSGroupAnalyzer.
2018-12-22 06:58:24 +00:00
whitequark
98a9744be4
hdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 06:03:39 +00:00
whitequark
8730895d8c
hdl.mem: allow changing init value after creating memory.
2018-12-22 01:09:03 +00:00
whitequark
f6772759c8
hdl.ir: fix port propagation between siblings, in the other direction.
2018-12-22 00:31:31 +00:00
whitequark
a4183eba69
hdl.mem: use more informative signal naming for ports.
2018-12-21 23:55:02 +00:00
whitequark
913339c04a
hdl.ir: fix port propagation between siblings.
2018-12-21 23:53:18 +00:00
whitequark
fc7da1be2d
hdl.ir: do not flatten instances or collect ports from their statements.
...
This results in absurd behavior for memories.
2018-12-21 13:52:18 +00:00
whitequark
fa2af27bb0
hdl.mem: ensure transparent read port model has correct latency.
2018-12-21 13:01:08 +00:00
whitequark
af7db882c0
hdl.mem: use different naming for array signals.
...
It looks like [] is confusing gtkwave somehow.
2018-12-21 12:26:49 +00:00
whitequark
e58d9ec74d
hdl.mem: add simulation model for memory.
2018-12-21 11:54:32 +00:00
whitequark
c49211c76a
hdl.mem: add tests for all error conditions.
2018-12-21 06:07:16 +00:00
whitequark
a061bfaa6c
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
2018-12-21 04:22:16 +00:00
whitequark
b0bd7bfaca
hdl.ir: correctly handle named output and inout ports.
2018-12-21 04:03:03 +00:00
whitequark
6d9a6b5d84
hdl.mem: implement memories.
2018-12-21 01:53:32 +00:00
whitequark
f7fec804ec
ir: allow non-Signals in Instance ports.
2018-12-20 23:40:40 +00:00
whitequark
0f2c7e7161
compat: import genlib.record from Migen.
2018-12-18 20:04:22 +00:00
whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
7341d0d7ef
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
2018-12-18 16:13:29 +00:00
whitequark
c7f9386eab
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
2018-12-17 22:55:39 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
8c4de99c0d
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
2018-12-17 17:21:29 +00:00
whitequark
850674637a
back.rtlil: implement Array.
2018-12-17 01:15:23 +00:00
whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
015998eba9
hdl.dsl: add clock domain support.
2018-12-16 23:51:24 +00:00
whitequark
b2f828387a
hdl.dsl: cleanup. NFC.
2018-12-16 23:44:00 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
286a8009c8
compat.fhdl: reexport Array.
2018-12-16 10:39:54 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
80c5343600
hdl.ast: implement Array and ArrayProxy.
2018-12-15 17:16:31 +00:00
whitequark
f603b735e8
hdl.ast: improve ClockSignal, ResetSignal documentation.
2018-12-15 14:58:31 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
