Commit graph

26 commits

Author SHA1 Message Date
whitequark 474d46ced8 back.pysim: implement most operators and add tests. 2018-12-14 14:21:22 +00:00
whitequark d9aaf0114b back.pysim: close .vcd/.gtkw files on context manager exit. 2018-12-14 13:59:03 +00:00
whitequark 1655b59d1b back.pysim: show more legible names for processes in errors. 2018-12-14 13:50:19 +00:00
whitequark 625c55a3b8 back.pysim: throw exceptions back at processes. 2018-12-14 13:43:25 +00:00
whitequark 654722ce14 back.pysim: add gtkw traces even more robustly. 2018-12-14 13:43:08 +00:00
whitequark 7d3f7f277a back.pysim: accept (and evaluate) generator functions. 2018-12-14 13:32:30 +00:00
whitequark 7fc9f98b98 back.pysim: skip VCD signal population if VCD is not requested. 2018-12-14 13:32:30 +00:00
whitequark 3ad79ec690 back.pysim: allow processes to evaluate expressions. 2018-12-14 13:32:30 +00:00
whitequark dd00b5e2d6 back.pysim: more general clean-up. 2018-12-14 12:46:04 +00:00
whitequark 1b7f8c7950 back.pysim: general clean-up. 2018-12-14 12:22:03 +00:00
whitequark 105113f1d8 back.pysim: accept any valid assignments from processes. 2018-12-14 12:18:41 +00:00
whitequark 240a40c2c2 back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw. 2018-12-14 10:57:13 +00:00
whitequark b34c1a9ad0 back.pysim: undriven comb signals should return to reset value. 2018-12-14 09:12:38 +00:00
whitequark b58715c5dc ast, back.pysim: allow specifying user-defined decoders for signals. 2018-12-14 09:02:29 +00:00
whitequark bb843cb40c back.pysim: fix completely broken codegen for Switch. 2018-12-14 08:51:36 +00:00
whitequark 6aefd0c04c back.pysim: raise an exception if delta cycles blow a process deadline. 2018-12-14 08:10:21 +00:00
whitequark a10791e160 back.pysim: if requested, write a gtkw file with a useful preset. 2018-12-14 08:04:29 +00:00
whitequark cb998d891b back.pysim: explain how delta cycles work. 2018-12-14 07:26:26 +00:00
whitequark e4d08d2855 back.pysim: delay clock processes by one half period.
Makes it easier to see initial delta cycles.
2018-12-14 05:17:43 +00:00
whitequark 3bb7a87e0f back.pysim: implement "sync processes", like migen.sim generators. 2018-12-14 05:13:58 +00:00
whitequark d791b77cc8 back.pysim: allow suspending processes until a tick in a domain. 2018-12-14 04:33:06 +00:00
whitequark 3e59d857e1 back.pysim: use bare ints for signal values (-5% runtime). 2018-12-14 03:05:57 +00:00
whitequark b09f4b10ee back.pysim: collect handlers before running (-5% runtime). 2018-12-13 18:34:44 +00:00
whitequark a7ebc02bdd back.pysim: allow multiple registered handlers per signal. 2018-12-13 18:28:11 +00:00
whitequark 6a4004ef8d back.pysim: fix handling of process termination. 2018-12-13 18:17:58 +00:00
whitequark fb27c2520b back.pysim: new simulator backend (WIP). 2018-12-13 18:02:46 +00:00