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Author SHA1 Message Date
Irides 538c14116c sim.pysim: use "bench" as a top level root for testbench signals. 
Fixes #561.
 2021-12-16 15:46:05 +00:00
Catherine 810c19dde4 Revert "Add PEP 518 pyproject.toml." 
This reverts commit a2ef4cb6b8.

This broke editable installs (again) and has to be reverted due pip
issue pypa/pip#7953.

Fixes #663.
 2021-12-16 15:02:16 +00:00
Catherine 22c7453783 Revert "setup: add workaround for pypa/pip#7953." 
This reverts commit b1f5664b05.
 2021-12-16 15:02:16 +00:00
Ben Newhouse 55756e9568
examples/uart: acknowledging RX data should deassert RX ready. 2021-12-16 13:31:32 +00:00
Catherine 0169d47365 docs/changes: add simulation-related changes. 2021-12-16 08:04:02 +00:00
Irides b1f5664b05 setup: add workaround for pypa/pip#7953. 2021-12-14 16:03:31 +00:00
Catherine 847e46927b back.{verilog,rtlil}: fix commit d83c4a1b. 
The `ports` argument has been passed implicitly, via `**kwargs`, and
that was broken during the deprecation.

Closes #659.
 2021-12-14 10:47:04 +00:00
Catherine a6a13dd612 docs: add changelog. 2021-12-13 13:00:10 +00:00
Irides d83c4a1b21 back.{rtlil,verilog}: deprecate implicit ports. 
Fixes #630.
 2021-12-13 12:21:44 +00:00
Catherine 24c4da2b2f lib.fifo: clarify AsyncFIFO{,Buffered}.r_rst documentation. NFC. 2021-12-13 09:53:57 +00:00
Catherine 47c79cf3c8 docs: simplify. NFC. 2021-12-13 09:53:54 +00:00
Irides 40b92965c9 docs: cover amaranth.vendor. 2021-12-13 09:17:50 +00:00
modwizcode 1ee2482c6b sim: represent time internally as 1ps units 
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.
 2021-12-13 08:15:11 +00:00
Catherine fab9fb1fea Revert "CI: add CPython 3.11 to the build matrix." 
This reverts commit 6860a0629a.
 2021-12-13 07:58:01 +00:00
Catherine 6860a0629a CI: add CPython 3.11 to the build matrix. 2021-12-13 07:55:46 +00:00
modwizcode d2c569c45e docs: cover amaranth.lib.fifo. 2021-12-13 07:48:43 +00:00
Catherine 2adbe59e4f docs: formatting and readability improvements. 2021-12-13 06:33:36 +00:00
Catherine 18837b9029 docs: cover amaranth.lib.cdc. 2021-12-13 06:23:12 +00:00
Catherine 3a8cd63b23 docs: cover amaranth.lib.coding. 2021-12-13 05:48:31 +00:00
Catherine 25163364d8 README: point IRC link to web.libera.chat. 2021-12-13 02:19:04 +00:00
Irides 0b74d1c5f6 back.rtlil: support slicing on Parts 
Fixes #605.
 2021-12-11 16:44:29 +00:00
whitequark 7c161957bf build.dsl: check type of resource number. 
Fixes #599.
 2021-12-11 13:37:15 +00:00
whitequark 7e2b72826f sim.core: warn when driving a clock domain not in the simulation. 
Closes #566.
 2021-12-11 13:22:24 +00:00
whitequark ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
 2021-12-11 13:00:46 +00:00
whitequark 599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. 
Fixes #592.
 2021-12-11 12:40:05 +00:00
whitequark 90777a65c8 build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*. 
These have been mistakenly omitted from commit 909a3b8b.
 2021-12-11 12:40:05 +00:00
Irides b1eba5fd82 vendor.xilinx: support setting options on synth_design 
Closes #606.
 2021-12-11 12:09:09 +00:00
whitequark fd7d01ef10 back.rtlil,cli: allow suppressing generation of src attributes. 
Fixes #572.
 2021-12-11 11:38:40 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. 
Closes #595.
 2021-12-11 11:12:25 +00:00
whitequark b452e0e871 hdl.ast: support division and modulo with negative divisor. 
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
 2021-12-11 10:25:48 +00:00
whitequark 25573c5eff back.rtlil: extend unsigned operand of binop if another is signed. 
Fixes #580.
 2021-12-11 10:25:48 +00:00
whitequark 44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). 
Fixes #639.
 2021-12-11 08:18:33 +00:00
whitequark de7c9acb19 _utils: don't crash trying to flatten() strings. 
Fixes #614.
 2021-12-11 07:39:35 +00:00
whitequark 0fb2b4cd39 docs: fix download link in start.rst. 
Fixes #647.
 2021-12-11 06:32:32 +00:00
whitequark 116d4b9bc2 nmigen.cli: add missing imports. 2021-12-10 17:16:32 +00:00
whitequark 4d83e13103 CI: fix test discovery command. 2021-12-10 10:48:14 +00:00
whitequark a7fdf661cf CI: only discover tests under tests/. 
This avoids a crash importing the deprecated `nmigen` module with
PYTHONWARNINGS=error set.
 2021-12-10 10:45:05 +00:00
whitequark e11d033b0f README: update header. 2021-12-10 10:42:15 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
whitequark 0b28a97ca0 CI: preserve YoWASP cache as well. 2021-11-05 19:08:21 +00:00
whitequark e91a5ad934 _toolchain.cxx: ignore another deprecation warning (on Python 3.10). 
Sigh.
 2021-11-05 19:03:46 +00:00
whitequark 3379f072a0 _toolchain.cxx: ignore deprecation warning (on Python 3.6). 
This code really shouldn't be using distutils, but for now this will
have to do.
 2021-11-05 18:58:26 +00:00
whitequark 369cc59d69 docs: update requirements. 
Sphinx 4.2 or later is required for compatibility with Python 3.10.

A released version of Pygments can now be used for highlighting.
 2021-11-05 18:53:09 +00:00
whitequark 8081df1265 _toolchain.cxx: use distutils from setuptools. 
The distutils module from the standard library is deprecated and will
be removed in Python 3.12, and PEP 632 recommends using
distutils.ccompiler from setuptools, instead.

This code should eventually be rewritten to use zig-pypi, but for now
this suffices.
 2021-11-05 18:48:50 +00:00
whitequark 97aa7a3aa9 vendor.xilinx_*: deprecate legacy Xilinx platform aliases. 2021-11-05 18:43:27 +00:00
whitequark f0af0a8449 Run tests on Python 3.10. 2021-11-05 18:40:45 +00:00
whitequark 7c740a85ea Simplify CI workflow. 2021-11-05 18:37:51 +00:00
whitequark a2ef4cb6b8 Add PEP 518 pyproject.toml. 2021-11-05 14:44:31 +00:00
Olivier Galibert 177f1b2e40
vendor.intel: add Mistral toolchain support. 2021-10-14 16:02:22 +00:00
whitequark 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__. 
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
 2021-10-03 20:28:07 +00:00