whitequark
|
5a831ce31c
|
lib.fifo: add basic formal specification.
|
2019-01-17 05:40:25 +00:00 |
|
|
whitequark
|
fa8e876356
|
hdl.ast: allow sampling ClockSignal, ResetSignal.
|
2019-01-17 05:23:06 +00:00 |
|
|
whitequark
|
8c96675580
|
hdl.ast: add Past, Stable, Rose, Fell.
|
2019-01-17 04:31:27 +00:00 |
|
|
whitequark
|
198efcad31
|
hdl.xfrm: add SampleLowerer.
|
2019-01-17 01:41:02 +00:00 |
|
|
whitequark
|
b3de114d67
|
hdl.ast: add Sample.
|
2019-01-17 01:36:27 +00:00 |
|
|
whitequark
|
b78a2be9f6
|
lib.fifo: port sync FIFO queues from Migen.
|
2019-01-16 17:20:38 +00:00 |
|
|
whitequark
|
cb2f18ee37
|
hdl.ast: fix naming of Signal.like() signals when tracer fails.
|
2019-01-16 17:20:38 +00:00 |
|
|
whitequark
|
b534e92dd5
|
hdl.ir: allow explicitly requesting flattening.
|
2019-01-14 17:04:23 +00:00 |
|
|
whitequark
|
011bf2258e
|
hdl: make ClockSignal and ResetSignal usable on LHS.
Fixes #8.
|
2019-01-14 15:38:16 +00:00 |
|
|
whitequark
|
664b4bcb3a
|
hdl.dsl: cases wider than switch test value are unreachable.
In 3083c1d6 they were erroneously fixed via truncation.
|
2019-01-13 08:51:49 +00:00 |
|
|
whitequark
|
3083c1d6dd
|
hdl.dsl: accept (but warn on) cases wider than switch test value.
Fixes #13.
|
2019-01-13 08:46:28 +00:00 |
|
|
whitequark
|
cbf7bd6e31
|
back.pysim: handle non-driven, non-port signals.
Fixes #20.
|
2019-01-13 08:31:38 +00:00 |
|
|
William D. Jones
|
2412650f56
|
hdl.dsl: Support Assert and Assume where an Assign can occur.
|
2019-01-02 11:17:39 +00:00 |
|
|
whitequark
|
3c07d8d52c
|
hdl.rec: include record name in error message.
|
2019-01-01 03:39:12 +00:00 |
|
|
whitequark
|
031a9e2616
|
hdl.rec: use a helpful error on unknown field reference.
|
2019-01-01 03:35:34 +00:00 |
|
|
whitequark
|
d78e6c155b
|
hdl.mem: add DummyPort, for testing and verification.
|
2019-01-01 03:08:10 +00:00 |
|
|
whitequark
|
39eb2e8fa7
|
lib.cdc: fix tests to actually run.
|
2018-12-29 15:02:44 +00:00 |
|
|
whitequark
|
849c649259
|
back.pysim: warn if simulation is not run.
This would have prevented 3ea35b85.
|
2018-12-29 15:02:04 +00:00 |
|
|
whitequark
|
92a96e1644
|
hdl.rec: add basic record support.
|
2018-12-28 13:22:10 +00:00 |
|
|
whitequark
|
3ea35b8566
|
lib.coding: fix tests to actually run, and fix code to fix tests.
|
2018-12-27 21:45:55 +00:00 |
|
|
whitequark
|
470d66934f
|
hdl.dsl: add support for fsm.ongoing().
|
2018-12-27 16:19:01 +00:00 |
|
|
whitequark
|
528747703d
|
lib.coding: port from Migen.
|
2018-12-26 13:19:34 +00:00 |
|
|
whitequark
|
fe8cb55204
|
lib.cdc: add tests for MultiReg.
|
2018-12-26 12:58:30 +00:00 |
|
|
whitequark
|
35a44f017f
|
hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
|
2018-12-26 12:42:43 +00:00 |
|
|
whitequark
|
934546e633
|
hdl.dsl: provide generated values for FSMs.
|
2018-12-26 12:39:05 +00:00 |
|
|
whitequark
|
040811c2e5
|
hdl.ir: add an API for retrieving generated values, like FSM signal.
This is useful for tests.
|
2018-12-26 12:35:35 +00:00 |
|
|
whitequark
|
54e3195dcb
|
hdl.dsl: implement FSM.
|
2018-12-26 08:55:04 +00:00 |
|
|
whitequark
|
98f554aa08
|
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
|
2018-12-24 02:17:28 +00:00 |
|
|
whitequark
|
1c7c75a254
|
hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
|
2018-12-24 02:02:59 +00:00 |
|
|
whitequark
|
621dddebfd
|
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
|
2018-12-22 22:19:14 +00:00 |
|
|
whitequark
|
68dae9f50e
|
hdl.ir: flatten hierarchy based on memory accesses, too.
|
2018-12-22 21:43:46 +00:00 |
|
|
whitequark
|
ae0cb48fbb
|
hdl.xfrm: implement LHSGroupAnalyzer.
|
2018-12-22 06:58:24 +00:00 |
|
|
whitequark
|
f6772759c8
|
hdl.ir: fix port propagation between siblings, in the other direction.
|
2018-12-22 00:31:31 +00:00 |
|
|
whitequark
|
913339c04a
|
hdl.ir: fix port propagation between siblings.
|
2018-12-21 23:53:18 +00:00 |
|
|
whitequark
|
fa2af27bb0
|
hdl.mem: ensure transparent read port model has correct latency.
|
2018-12-21 13:01:08 +00:00 |
|
|
whitequark
|
48d13e47ec
|
back.pysim: handle out of bounds ArrayProxy indexes.
|
2018-12-21 12:32:08 +00:00 |
|
|
whitequark
|
e58d9ec74d
|
hdl.mem: add simulation model for memory.
|
2018-12-21 11:54:32 +00:00 |
|
|
whitequark
|
c49211c76a
|
hdl.mem: add tests for all error conditions.
|
2018-12-21 06:07:16 +00:00 |
|
|
whitequark
|
b0bd7bfaca
|
hdl.ir: correctly handle named output and inout ports.
|
2018-12-21 04:03:03 +00:00 |
|
|
whitequark
|
f7fec804ec
|
ir: allow non-Signals in Instance ports.
|
2018-12-20 23:40:40 +00:00 |
|
|
whitequark
|
dbbcc49a71
|
hdl.ast: Cat.{operands→parts}
|
2018-12-18 19:15:50 +00:00 |
|
|
whitequark
|
4199674edd
|
back.pysim: implement *.
|
2018-12-18 18:02:21 +00:00 |
|
|
whitequark
|
07e9cfa939
|
test.sim: add tests for sync functionality and errors.
|
2018-12-18 17:53:50 +00:00 |
|
|
whitequark
|
c7f9386eab
|
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
|
2018-12-17 22:55:39 +00:00 |
|
|
whitequark
|
8d1639a5a8
|
hdl, back: add and use SignalSet/SignalDict.
|
2018-12-17 17:21:29 +00:00 |
|
|
whitequark
|
015998eba9
|
hdl.dsl: add clock domain support.
|
2018-12-16 23:51:24 +00:00 |
|
|
whitequark
|
d4e8d3e95a
|
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
|
2018-12-16 10:31:42 +00:00 |
|
|
whitequark
|
d9579219ee
|
test.sim: generalize assertOperator. NFC.
|
2018-12-15 21:08:29 +00:00 |
|
|
whitequark
|
20a04bca88
|
back.pysim: implement Part.
|
2018-12-15 20:58:06 +00:00 |
|
|
whitequark
|
54fb999c99
|
back.pysim: implement ArrayProxy.
|
2018-12-15 19:37:36 +00:00 |
|