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Author SHA1 Message Date
whitequark 003ba3b45f hdl.cd: implement local clock domains. 
Closes #175.
 2019-08-19 21:44:33 +00:00
whitequark 9bdadbff09 back.pysim: index domains by identity, not by name. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:44:33 +00:00
whitequark 69d36dc139 hdl.xfrm: lower resets in DomainLowerer as well. 
Changed in preparation for introducing local clock domains.

Also makes elaboration about 15% faster.
 2019-08-19 21:44:30 +00:00
whitequark 404f99f022 hdl.xfrm: consider fragment's own domains in DomainLowerer. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:07:02 +00:00
whitequark 32bfbb11cb formal→asserts 
Closes #171.
 2019-08-19 20:23:24 +00:00
whitequark 2770db6de8 tracer: fix typo. 
Introduced in 62b3e366.
 2019-08-19 20:20:18 +00:00
whitequark ada1d6a603 build.plat: do not prepare fragments twice. 
Fixes #169.
 2019-08-19 19:49:51 +00:00
whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). 
Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
 2019-08-19 19:49:51 +00:00
Robin Heinemann 8e048c5a7c build.dsl: add conn argument to Connector. 2019-08-18 19:56:25 +00:00
whitequark 84f2c3df2b compat.fhdl.decorators: avoid using deprecated NativeCEInserter. 2019-08-18 16:27:11 +00:00
whitequark d44ea4e9fe hdl.xfrm: make deprecated CEInserter more well-behaved. 2019-08-18 16:26:45 +00:00
whitequark ed7e07c6c1 hdl.ast: implement Initial. 
This is the last remaining part for first-class formal support.
 2019-08-15 02:53:07 +00:00
whitequark 40abaef858 hdl.xfrm: sample cache should be per-fragment. 2019-08-15 02:45:31 +00:00
whitequark fa0fa056ba hdl.xfrm: CEInserter→EnableInserter. 
Fixes #166.
 2019-08-12 13:39:26 +00:00
whitequark 9d2cbbabb8 hdl.ast: hash-cons ValueKey. 
This speeds up elaboration by ~10%.
 2019-08-08 10:56:53 +00:00
whitequark 4ee82c9584 tracer: use sys._getframe directly. 
This speeds up elaboration by ~30-40%.
 2019-08-08 10:23:35 +00:00
whitequark e6b1e3de1a compat.fhdl.decorators: port from oMigen. 2019-08-08 08:09:28 +00:00
whitequark 5c626e33bf compat.fhdl.module: fix finalization of transformed compat submodules. 
Before this commit, the TransformedElaboratable of a CompatModule
would be ignored, and .get_fragment() would be used to retrieve
the CompatModule within.

After this commit, the finalization process is reworked to match
oMigen's finalization closely, and all submodules, native and compat,
are added in the same way that preserves applied transforms.
 2019-08-08 07:45:34 +00:00
whitequark 1b379a513c vendor.lattice_ice40: add iCE5LP2K support. 2019-08-07 09:25:20 +00:00
whitequark cfbc678508 vendor.lattice_ice40: add iCE40UP3K support. 2019-08-07 09:06:27 +00:00
whitequark 9c35e44e4a vendor.lattice_ice40: add iCE5LP1K support. 2019-08-07 09:01:11 +00:00
whitequark 434b686d5e vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic. 
On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.
 2019-08-04 23:28:09 +00:00
whitequark 3d7214cb70 vendor.xilinx_spartan_3_6: reconsider bitgen defaults. 
Previously changed in 27063a3b.

I haven't realized the .bin file is the same as the .bit file without
a small header. That means generating it is free and it's just easier
to let programming tools to be able to always rely on its existence.
 2019-08-04 23:28:09 +00:00
whitequark 27063a3bd3 vendor.xilinx_spartan_3_6: set bitgen defaults to -g Binary:Yes -g Compress. 
* `-g Binary:Yes` should be overridable.
  * `-g Compress` is a good default.
 2019-08-04 14:18:49 +00:00
whitequark 65da905c15 vendor.xilinx_spartan_3_6: always use -w for map/par/bitgen. 
-w stands for "override output file", and supplying user options
should not remove it.
 2019-08-04 14:12:02 +00:00
whitequark 15e8dfe532 vendor.xilinx_spartan_3_6: do not use retiming by default. 
This was added in b404d603, probably by mistake, and is certainly
wrong given that we do not (yet) correctly mark CDC FFs.
 2019-08-04 13:48:33 +00:00
whitequark 6b025df12c vendor.xilinx_spartan_3_6: force use of bash on UNIX. 2019-08-04 13:20:54 +00:00
whitequark 5eb4e2ee51 build.plat: allow selecting a specific UNIX shell interpreter. 
Mostly because vendor tools have bashisms.
 2019-08-04 13:20:54 +00:00
whitequark 34a97b2751 vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins. 2019-08-04 00:30:50 +00:00
whitequark 2e6627c4af back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. 
Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.

(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
 2019-08-04 00:12:08 +00:00
whitequark d0ac8bf789 back.rtlil: actually match shape of left hand side. 
This comes up in code such as:
  Array([Signal(1), Signal(8)]).eq(Const(0, 8))
 2019-08-03 23:48:28 +00:00
whitequark 999a2f612a vendor.lattice_ice40: add missing signal indexing. 2019-08-03 22:59:33 +00:00
whitequark 8dd54ac544 build.run: use keyword-only arguments where appropriate. 2019-08-03 22:52:58 +00:00
whitequark 0fe05188e8 compat.fhdl.specials: track changes in build.plat. 2019-08-03 22:52:34 +00:00
whitequark 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear. 
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
 2019-08-03 18:52:24 +00:00
whitequark 8854ca03ae build.plat,vendor: automatically create sync domain from default_clk. 
But only if it is not defined by the programmer.

Closes #57.
 2019-08-03 18:36:58 +00:00
whitequark e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback. 
This is useful for injecting complex power-on reset logic.
 2019-08-03 18:19:40 +00:00
whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. 
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
 2019-08-03 16:39:21 +00:00
whitequark 21f2f8c46e build.plat: add default_rst, to be used with default_clk. 2019-08-03 16:28:03 +00:00
whitequark 4dbb5352ad build.plat: add default_clk{,_constraint,_frequency}. 
This is the equivalent of oMigen's default_clk and default_clk_period
except the period is taken from the resource.
 2019-08-03 16:18:46 +00:00
whitequark cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback. 
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.
 2019-08-03 15:44:02 +00:00
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. 
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
 2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):. 
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.

Fixes #159.
 2019-08-03 14:00:29 +00:00
whitequark ab5426ce74 Improve test added in 29fee01f to not leak warnings. 2019-08-03 13:44:44 +00:00
whitequark ee03eab52f back.rtlil: fix sim-synth mismatch with assigns following switches. 
Closes #155.
 2019-08-03 13:27:47 +00:00
whitequark 0a603b3844 hdl.ast: fix typo. 2019-08-03 13:21:09 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. 
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
 2019-08-03 12:51:57 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00