whitequark
65702719e8
back.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 04:43:04 +00:00
whitequark
34b81d0b87
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
2018-12-18 04:37:39 +00:00
whitequark
d6e98fd934
back.pysim: continue running simulator processes until they suspend.
2018-12-18 03:05:16 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
bdb8db2826
back.pysim: add (stub) LHSValueCompiler.
2018-12-15 21:01:38 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
3a8685c352
Consistently use '{!r}' in and only in TypeError messages.
2018-12-15 09:31:58 +00:00
whitequark
7108111ad0
back.pysim: preserve process locations through add_sync_process().
2018-12-14 23:27:36 +00:00
whitequark
0015713bfb
back.pysim: count delta cycles separately to avoid clock drift.
2018-12-14 20:52:41 +00:00
whitequark
a6a8703a0e
back.pysim: simplify.
2018-12-14 20:45:45 +00:00
whitequark
7e3cf26cf8
back.pysim: revert 70ebc6f2.
2018-12-14 19:46:08 +00:00
whitequark
71304c9fe7
back.pysim: fix implicit boolean conversion.
2018-12-14 19:08:06 +00:00
whitequark
fe5fb34fae
back.pysim: squash one level of hierarchy.
...
There's really no point in the "top" node.
2018-12-14 18:53:21 +00:00
whitequark
70ebc6f2c1
back.pysim: implement blocking assignment semantics correctly.
2018-12-14 18:47:12 +00:00
whitequark
120d817123
back.pysim: undriven sync signals should return to previous value.
2018-12-14 17:25:48 +00:00
whitequark
4f5b4a9bf4
back.pysim: in simulator sync processes, start by waiting for a tick.
...
This matches Migen behavior and also makes more sense.
2018-12-14 17:05:11 +00:00
whitequark
e230383aac
back.pysim: make initial phase configurable.
2018-12-14 16:46:16 +00:00
whitequark
88970ee29f
pysim.back: fix add_sync_process wrapper to handle signals correctly.
2018-12-14 16:21:53 +00:00
whitequark
9307a31678
back.pysim: Simulator({gtkw_signals→traces}=).
2018-12-14 15:23:22 +00:00
whitequark
e3f32a1faf
back.pysim: better naming. NFC.
2018-12-14 15:21:13 +00:00
whitequark
474d46ced8
back.pysim: implement most operators and add tests.
2018-12-14 14:21:22 +00:00
whitequark
d9aaf0114b
back.pysim: close .vcd/.gtkw files on context manager exit.
2018-12-14 13:59:03 +00:00
whitequark
1655b59d1b
back.pysim: show more legible names for processes in errors.
2018-12-14 13:50:19 +00:00
whitequark
625c55a3b8
back.pysim: throw exceptions back at processes.
2018-12-14 13:43:25 +00:00
whitequark
654722ce14
back.pysim: add gtkw traces even more robustly.
2018-12-14 13:43:08 +00:00
whitequark
7d3f7f277a
back.pysim: accept (and evaluate) generator functions.
2018-12-14 13:32:30 +00:00
whitequark
7fc9f98b98
back.pysim: skip VCD signal population if VCD is not requested.
2018-12-14 13:32:30 +00:00
whitequark
3ad79ec690
back.pysim: allow processes to evaluate expressions.
2018-12-14 13:32:30 +00:00
whitequark
dd00b5e2d6
back.pysim: more general clean-up.
2018-12-14 12:46:04 +00:00
whitequark
1b7f8c7950
back.pysim: general clean-up.
2018-12-14 12:22:03 +00:00
whitequark
105113f1d8
back.pysim: accept any valid assignments from processes.
2018-12-14 12:18:41 +00:00
whitequark
240a40c2c2
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
2018-12-14 10:57:13 +00:00
whitequark
b34c1a9ad0
back.pysim: undriven comb signals should return to reset value.
2018-12-14 09:12:38 +00:00
whitequark
b58715c5dc
ast, back.pysim: allow specifying user-defined decoders for signals.
2018-12-14 09:02:29 +00:00
whitequark
bb843cb40c
back.pysim: fix completely broken codegen for Switch.
2018-12-14 08:51:36 +00:00
whitequark
6aefd0c04c
back.pysim: raise an exception if delta cycles blow a process deadline.
2018-12-14 08:10:21 +00:00
whitequark
a10791e160
back.pysim: if requested, write a gtkw file with a useful preset.
2018-12-14 08:04:29 +00:00
whitequark
cb998d891b
back.pysim: explain how delta cycles work.
2018-12-14 07:26:26 +00:00
whitequark
e4d08d2855
back.pysim: delay clock processes by one half period.
...
Makes it easier to see initial delta cycles.
2018-12-14 05:17:43 +00:00
whitequark
3bb7a87e0f
back.pysim: implement "sync processes", like migen.sim generators.
2018-12-14 05:13:58 +00:00
whitequark
d791b77cc8
back.pysim: allow suspending processes until a tick in a domain.
2018-12-14 04:33:06 +00:00
whitequark
3e59d857e1
back.pysim: use bare ints for signal values (-5% runtime).
2018-12-14 03:05:57 +00:00
whitequark
b09f4b10ee
back.pysim: collect handlers before running (-5% runtime).
2018-12-13 18:34:44 +00:00
whitequark
a7ebc02bdd
back.pysim: allow multiple registered handlers per signal.
2018-12-13 18:28:11 +00:00
whitequark
6a4004ef8d
back.pysim: fix handling of process termination.
2018-12-13 18:17:58 +00:00
