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Author SHA1 Message Date
Catherine
9a5a6142d9 setup: relax pyvcd version constraint to >=0.2.2,<0.4. 
Fixes #690.
 2022-04-04 09:21:11 +00:00
Irides
85d56a74a5 build.plat,setup: fix Jinja2 dependency. 
Jinja2 version 2.11 has a broken dependency constraint that allows its
dependency on markupsafe to pull in a version that it is not actually
compatible with the interface of. Fix this by upgrading the dependency
to `~=3.0`. This requires a small patch to the code to replace the
deprecated `@jinja2.contextfunction` decorator with the replacement
`@jinja2.pass_context`since `@jinja2.contextfunction` is removed in
Jinja2 version 3.1.0.
 2022-03-30 21:38:58 +00:00
Jean-François Nguyen
f6253b3851 build.plat: use tool_env_var() in _toolchain_env_var. 2022-03-29 21:04:51 +00:00
Catherine
1f1d189441 build.run: pipeline SFTP operations to improve performance. 2022-03-17 05:38:58 +00:00
Catherine
4dea0b2d0f vendor.lattice_ecp5: on Diamond, only emit attributes if there are any. 2022-03-12 13:25:00 +00:00
Bastian Löher
02364a4fd7 sim: Fix clock phase in add_clock having to be specified in ps. 2022-02-04 16:46:52 +00:00
Alyssa Rosenzweig
c83b51db6d back.verilog: Fix strip_internal_attrs 
Fix the strip_internal_attrs parameter to verilog.convert by passing it
down the call stack as intended.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2022-01-27 06:42:59 +00:00
Tobias Müller
c6dc08cbdd
setup: loosen dependency on Jinja2 version. 2022-01-17 19:28:46 +00:00
Catherine
7d611b8fc1 docs: update sphinxcontrib-platformpicker. 2022-01-02 05:19:50 +00:00
Catherine
4ae75c117f docs/tutorial: remove dead link. 2022-01-02 04:41:33 +00:00
Irides
5a4d45b599
back.rtlil: avoid sync process emission in RTLIL. 
Avoiding emission of sync processes in RTLIL allows us to avoid a dependency on
matching the behavior expected by Yosys, which generally expects sync processes
in RTLIL to match those emitted by the output from its own Verilog parser.
This also simplifies the logic used in emitting RTLIL overall.

Combinatorial processes are still emitted however. Without these the RTLIL does
not have a high-level understanding of Switch statements, which significantly
diminishes the quality of emitted Verilog, as these are converted to `$mux`
cells in Yosys, which become `?` constructs when converted back to Verilog.

Fixes #603.
Fixes #672.
 2022-01-01 18:18:33 +00:00
Catherine
aa749567e4 docs: update sphinx-rtd-theme. 
Incorporate the fix for readthedocs/sphinx_rtd_theme#1168.
 2021-12-28 20:43:15 +00:00
Catherine
39a83f4d99 setup: fix documentation URL for releases. 2021-12-16 18:02:11 +00:00
Catherine
e2b3e8caf9 CI: publish documentation at https://amaranth-lang.org/docs/amaranth/ 2021-12-16 17:51:53 +00:00
Catherine
a243e0443e CI: publish documentation for tagged commits. 2021-12-16 17:46:01 +00:00
Catherine
e156ac62c5 docs: don't call Python modules "packages". 2021-12-16 17:46:01 +00:00
Irides
538c14116c sim.pysim: use "bench" as a top level root for testbench signals. 
Fixes #561.
 2021-12-16 15:46:05 +00:00
Catherine
810c19dde4 Revert "Add PEP 518 pyproject.toml." 
This reverts commit a2ef4cb6b8.

This broke editable installs (again) and has to be reverted due pip
issue pypa/pip#7953.

Fixes #663.
 2021-12-16 15:02:16 +00:00
Catherine
22c7453783 Revert "setup: add workaround for pypa/pip#7953." 
This reverts commit b1f5664b05.
 2021-12-16 15:02:16 +00:00
Ben Newhouse
55756e9568
examples/uart: acknowledging RX data should deassert RX ready. 2021-12-16 13:31:32 +00:00
Catherine
0169d47365 docs/changes: add simulation-related changes. 2021-12-16 08:04:02 +00:00
Irides
b1f5664b05 setup: add workaround for pypa/pip#7953. 2021-12-14 16:03:31 +00:00
Catherine
847e46927b back.{verilog,rtlil}: fix commit d83c4a1b. 
The `ports` argument has been passed implicitly, via `**kwargs`, and
that was broken during the deprecation.

Closes #659.
 2021-12-14 10:47:04 +00:00
Catherine
a6a13dd612 docs: add changelog. 2021-12-13 13:00:10 +00:00
Irides
d83c4a1b21 back.{rtlil,verilog}: deprecate implicit ports. 
Fixes #630.
 2021-12-13 12:21:44 +00:00
Catherine
24c4da2b2f lib.fifo: clarify AsyncFIFO{,Buffered}.r_rst documentation. NFC. 2021-12-13 09:53:57 +00:00
Catherine
47c79cf3c8 docs: simplify. NFC. 2021-12-13 09:53:54 +00:00
Irides
40b92965c9 docs: cover amaranth.vendor. 2021-12-13 09:17:50 +00:00
modwizcode
1ee2482c6b sim: represent time internally as 1ps units 
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.
 2021-12-13 08:15:11 +00:00
Catherine
fab9fb1fea Revert "CI: add CPython 3.11 to the build matrix." 
This reverts commit 6860a0629a.
 2021-12-13 07:58:01 +00:00
Catherine
6860a0629a CI: add CPython 3.11 to the build matrix. 2021-12-13 07:55:46 +00:00
modwizcode
d2c569c45e docs: cover amaranth.lib.fifo. 2021-12-13 07:48:43 +00:00
Catherine
2adbe59e4f docs: formatting and readability improvements. 2021-12-13 06:33:36 +00:00
Catherine
18837b9029 docs: cover amaranth.lib.cdc. 2021-12-13 06:23:12 +00:00
Catherine
3a8cd63b23 docs: cover amaranth.lib.coding. 2021-12-13 05:48:31 +00:00
Catherine
25163364d8 README: point IRC link to web.libera.chat. 2021-12-13 02:19:04 +00:00
Irides
0b74d1c5f6 back.rtlil: support slicing on Parts 
Fixes #605.
 2021-12-11 16:44:29 +00:00
whitequark
7c161957bf build.dsl: check type of resource number. 
Fixes #599.
 2021-12-11 13:37:15 +00:00
whitequark
7e2b72826f sim.core: warn when driving a clock domain not in the simulation. 
Closes #566.
 2021-12-11 13:22:24 +00:00
whitequark
ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
 2021-12-11 13:00:46 +00:00
whitequark
599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. 
Fixes #592.
 2021-12-11 12:40:05 +00:00
whitequark
90777a65c8 build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*. 
These have been mistakenly omitted from commit 909a3b8b.
 2021-12-11 12:40:05 +00:00
Irides
b1eba5fd82 vendor.xilinx: support setting options on synth_design 
Closes #606.
 2021-12-11 12:09:09 +00:00
whitequark
fd7d01ef10 back.rtlil,cli: allow suppressing generation of src attributes. 
Fixes #572.
 2021-12-11 11:38:40 +00:00
whitequark
66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. 
Closes #595.
 2021-12-11 11:12:25 +00:00
whitequark
b452e0e871 hdl.ast: support division and modulo with negative divisor. 
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
 2021-12-11 10:25:48 +00:00
whitequark
25573c5eff back.rtlil: extend unsigned operand of binop if another is signed. 
Fixes #580.
 2021-12-11 10:25:48 +00:00
whitequark
44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). 
Fixes #639.
 2021-12-11 08:18:33 +00:00
whitequark
de7c9acb19 _utils: don't crash trying to flatten() strings. 
Fixes #614.
 2021-12-11 07:39:35 +00:00
whitequark
0fb2b4cd39 docs: fix download link in start.rst. 
Fixes #647.
 2021-12-11 06:32:32 +00:00