whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
f968678937
back.rtlil: handle reset_less domains.
2018-12-16 23:52:47 +00:00
whitequark
015998eba9
hdl.dsl: add clock domain support.
2018-12-16 23:51:24 +00:00
whitequark
b2f828387a
hdl.dsl: cleanup. NFC.
2018-12-16 23:44:00 +00:00
whitequark
91b7561a00
back.rtlil: extract _StatementCompiler. NFC.
2018-12-16 22:26:58 +00:00
whitequark
b9a0af8bde
back.rtlil: simplify. NFC.
2018-12-16 21:00:00 +00:00
whitequark
635094350f
back.rtlil: properly escape strings in attributes.
2018-12-16 20:27:36 +00:00
whitequark
41d69c3ad7
README: mention Yosys requirement.
2018-12-16 18:09:11 +00:00
whitequark
33f32a25f5
back.rtlil: prepare for Yosys sigspec slicing improvements.
...
See YosysHQ/yosys#741 .
2018-12-16 18:03:14 +00:00
whitequark
db5fd1e4c4
compat.fhdl.structure: only convert to bool in If/Elif if necessary.
2018-12-16 17:41:42 +00:00
whitequark
9bce35098f
back.rtlil: avoid illegal slices.
...
Not sure what to do with {} [] on LHS yet--fix Yosys?
2018-12-16 17:41:11 +00:00
whitequark
e86104d3a6
back.rtlil: use slicing to match shape when reducing width.
2018-12-16 16:20:45 +00:00
whitequark
2833b36c73
back.rtlil: don't emit a slice if all bits are used.
2018-12-16 16:05:38 +00:00
whitequark
9794e732e2
back.rtlil: reorganize value compiler into LHS/RHS.
...
This also implements Cat on LHS.
2018-12-16 13:33:34 +00:00
whitequark
ed39748889
back.rtlil: fix naming. NFC.
2018-12-16 11:26:31 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
286a8009c8
compat.fhdl: reexport Array.
2018-12-16 10:39:54 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
d9579219ee
test.sim: generalize assertOperator. NFC.
2018-12-15 21:08:29 +00:00
whitequark
bdb8db2826
back.pysim: add (stub) LHSValueCompiler.
2018-12-15 21:01:38 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
1adf58f561
examples: rename clkdiv/ctrl to ctr/ctr_ce.
2018-12-15 20:42:52 +00:00
whitequark
6c601fecfa
doc: update COMPAT_SUMMARY.
2018-12-15 20:40:56 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
80c5343600
hdl.ast: implement Array and ArrayProxy.
2018-12-15 17:16:31 +00:00
whitequark
1580b6e542
Lower Python version requirement to 3.6.
2018-12-15 17:03:23 +00:00
whitequark
c6e7a93717
hdl: appropriately rename tests. NFC.
2018-12-15 16:13:53 +00:00
whitequark
f603b735e8
hdl.ast: improve ClockSignal, ResetSignal documentation.
2018-12-15 14:58:31 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
b5a1efa0c8
Move star imports to make from nmigen import * usable.
2018-12-15 14:20:10 +00:00
whitequark
ad3c88852f
doc: fix some Markdown awkwardness.
2018-12-15 12:07:56 +00:00
whitequark
cc96a7ecfa
doc: update COMPAT_SUMMARY to reflect actual status.
2018-12-15 12:04:52 +00:00
whitequark
1f10bd96b9
Determine Migen's API surface and document compatibility summary.
...
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
2018-12-15 11:52:30 +00:00
whitequark
b70340c0da
pyback.sim: test Slice, Cat, Repl.
2018-12-15 10:09:14 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
46f5addf05
fhdl.ast: refactor Operator.shape(). NFC.
2018-12-15 09:46:20 +00:00
whitequark
3a8685c352
Consistently use '{!r}' in and only in TypeError messages.
2018-12-15 09:31:58 +00:00
whitequark
f9f7921959
fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
2018-12-15 09:26:36 +00:00
whitequark
f5e8c9033d
fhdl.ir: fix incorrect uses of positive to say non-negative.
...
Also test Part and Slice properly.
2018-12-15 09:26:23 +00:00
whitequark
9010805040
compat.fhdl.structure: handle If/Elif with multi-bit condition.
2018-12-15 00:10:54 +00:00
whitequark
ecea721f43
compat.fhdl.module: allow adding native submodules to compat modules.
2018-12-14 23:56:50 +00:00
whitequark
1c7b43ea49
Fix deprecations in Python 3.7.
2018-12-14 23:56:50 +00:00
whitequark
7108111ad0
back.pysim: preserve process locations through add_sync_process().
2018-12-14 23:27:36 +00:00
whitequark
c4ba5a3915
fhdl.ast: clean up stub error messages. NFC.
2018-12-14 23:07:16 +00:00
whitequark
2001359b66
fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
...
Fixes #5 .
2018-12-14 22:48:17 +00:00
whitequark
579feaba4e
fhdl.ir: Fragment.{drive→add_driver}
2018-12-14 20:58:29 +00:00
whitequark
0015713bfb
back.pysim: count delta cycles separately to avoid clock drift.
2018-12-14 20:52:41 +00:00
whitequark
a6a8703a0e
back.pysim: simplify.
2018-12-14 20:45:45 +00:00
whitequark
7e3cf26cf8
back.pysim: revert 70ebc6f2.
2018-12-14 19:46:08 +00:00
whitequark
71304c9fe7
back.pysim: fix implicit boolean conversion.
2018-12-14 19:08:06 +00:00
