whitequark
f1e390cbc9
back.rtlil: update for Yosys master.
2018-12-17 15:50:43 +00:00
whitequark
850674637a
back.rtlil: implement Array.
2018-12-17 01:15:23 +00:00
whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
f968678937
back.rtlil: handle reset_less domains.
2018-12-16 23:52:47 +00:00
whitequark
91b7561a00
back.rtlil: extract _StatementCompiler. NFC.
2018-12-16 22:26:58 +00:00
whitequark
b9a0af8bde
back.rtlil: simplify. NFC.
2018-12-16 21:00:00 +00:00
whitequark
635094350f
back.rtlil: properly escape strings in attributes.
2018-12-16 20:27:36 +00:00
whitequark
33f32a25f5
back.rtlil: prepare for Yosys sigspec slicing improvements.
...
See YosysHQ/yosys#741 .
2018-12-16 18:03:14 +00:00
whitequark
9bce35098f
back.rtlil: avoid illegal slices.
...
Not sure what to do with {} [] on LHS yet--fix Yosys?
2018-12-16 17:41:11 +00:00
whitequark
e86104d3a6
back.rtlil: use slicing to match shape when reducing width.
2018-12-16 16:20:45 +00:00
whitequark
2833b36c73
back.rtlil: don't emit a slice if all bits are used.
2018-12-16 16:05:38 +00:00
whitequark
9794e732e2
back.rtlil: reorganize value compiler into LHS/RHS.
...
This also implements Cat on LHS.
2018-12-16 13:33:34 +00:00
whitequark
ed39748889
back.rtlil: fix naming. NFC.
2018-12-16 11:26:31 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
bdb8db2826
back.pysim: add (stub) LHSValueCompiler.
2018-12-15 21:01:38 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
3a8685c352
Consistently use '{!r}' in and only in TypeError messages.
2018-12-15 09:31:58 +00:00
whitequark
7108111ad0
back.pysim: preserve process locations through add_sync_process().
2018-12-14 23:27:36 +00:00
whitequark
0015713bfb
back.pysim: count delta cycles separately to avoid clock drift.
2018-12-14 20:52:41 +00:00
whitequark
a6a8703a0e
back.pysim: simplify.
2018-12-14 20:45:45 +00:00
whitequark
7e3cf26cf8
back.pysim: revert 70ebc6f2.
2018-12-14 19:46:08 +00:00
whitequark
71304c9fe7
back.pysim: fix implicit boolean conversion.
2018-12-14 19:08:06 +00:00
whitequark
fe5fb34fae
back.pysim: squash one level of hierarchy.
...
There's really no point in the "top" node.
2018-12-14 18:53:21 +00:00
whitequark
70ebc6f2c1
back.pysim: implement blocking assignment semantics correctly.
2018-12-14 18:47:12 +00:00
whitequark
120d817123
back.pysim: undriven sync signals should return to previous value.
2018-12-14 17:25:48 +00:00
whitequark
4f5b4a9bf4
back.pysim: in simulator sync processes, start by waiting for a tick.
...
This matches Migen behavior and also makes more sense.
2018-12-14 17:05:11 +00:00
whitequark
e230383aac
back.pysim: make initial phase configurable.
2018-12-14 16:46:16 +00:00
whitequark
88970ee29f
pysim.back: fix add_sync_process wrapper to handle signals correctly.
2018-12-14 16:21:53 +00:00
whitequark
9307a31678
back.pysim: Simulator({gtkw_signals→traces}=).
2018-12-14 15:23:22 +00:00
whitequark
e3f32a1faf
back.pysim: better naming. NFC.
2018-12-14 15:21:13 +00:00
whitequark
474d46ced8
back.pysim: implement most operators and add tests.
2018-12-14 14:21:22 +00:00
whitequark
d9aaf0114b
back.pysim: close .vcd/.gtkw files on context manager exit.
2018-12-14 13:59:03 +00:00
whitequark
1655b59d1b
back.pysim: show more legible names for processes in errors.
2018-12-14 13:50:19 +00:00
whitequark
625c55a3b8
back.pysim: throw exceptions back at processes.
2018-12-14 13:43:25 +00:00
whitequark
654722ce14
back.pysim: add gtkw traces even more robustly.
2018-12-14 13:43:08 +00:00
whitequark
7d3f7f277a
back.pysim: accept (and evaluate) generator functions.
2018-12-14 13:32:30 +00:00
whitequark
7fc9f98b98
back.pysim: skip VCD signal population if VCD is not requested.
2018-12-14 13:32:30 +00:00
whitequark
3ad79ec690
back.pysim: allow processes to evaluate expressions.
2018-12-14 13:32:30 +00:00
whitequark
dd00b5e2d6
back.pysim: more general clean-up.
2018-12-14 12:46:04 +00:00
whitequark
1b7f8c7950
back.pysim: general clean-up.
2018-12-14 12:22:03 +00:00
whitequark
105113f1d8
back.pysim: accept any valid assignments from processes.
2018-12-14 12:18:41 +00:00
whitequark
240a40c2c2
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
2018-12-14 10:57:13 +00:00
whitequark
b34c1a9ad0
back.pysim: undriven comb signals should return to reset value.
2018-12-14 09:12:38 +00:00
whitequark
b58715c5dc
ast, back.pysim: allow specifying user-defined decoders for signals.
2018-12-14 09:02:29 +00:00
whitequark
bb843cb40c
back.pysim: fix completely broken codegen for Switch.
2018-12-14 08:51:36 +00:00
whitequark
6aefd0c04c
back.pysim: raise an exception if delta cycles blow a process deadline.
2018-12-14 08:10:21 +00:00
