Commit graph

18 commits

Author SHA1 Message Date
whitequark 53bb4300a3 build.plat: strip internal attributes from Verilog output.
Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.

This still leaves the (*init*) attribute. See #220 for details.
2019-09-24 14:56:00 +00:00
whitequark d1779bdb59 back: return name map from convert_fragment(). 2019-09-11 23:22:12 +00:00
Emily c4e8ac734f _toolchain,build.plat,vendor.*: add required_tools list and checks. 2019-08-31 00:05:47 +00:00
whitequark b14f5572d8 _toolchain: new module, for injecting dependencies in e.g. Nix. 2019-08-28 11:32:18 +00:00
whitequark 2168ff512b back.verilog: bump Yosys version requirement to 0.9.
Fixes #55.
2019-08-26 09:59:40 +00:00
whitequark 5ad409e897 back.verilog: parse output of yosys -V.
See #55.
2019-08-19 23:28:33 +00:00
whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert().
Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
2019-08-19 19:49:51 +00:00
whitequark 10e56c75fb back.verilog: run proc_prune for much cleaner output.
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@44bcb7a1.
2019-07-09 19:28:09 +00:00
whitequark 97af266645 back.verilog: allow stripping the src attribute, for cleaner output. 2019-04-22 14:59:53 +00:00
whitequark 06faeee357 back.verilog: better error message if Yosys is not found.
Fixes #17.
2019-01-13 08:10:23 +00:00
whitequark 307de722cb back.verilog: remove undriven check.
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.
2019-01-08 22:43:09 +00:00
whitequark 6ee80408bb back.verilog: do not rename internal signals.
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
2018-12-22 00:53:40 +00:00
whitequark a061bfaa6c hdl.mem: tie rdport.en high for asynchronous or transparent ports. 2018-12-21 04:22:16 +00:00
whitequark 2b4a8510ca back.rtlil: implement memories. 2018-12-21 01:55:59 +00:00
whitequark ac498414ab back.verilog: remove debug code. 2018-12-13 13:42:54 +00:00
whitequark 6251c95d4e compat.genlib.fsm: import/wrap Migen code. 2018-12-13 12:41:19 +00:00
whitequark 4e32f6b8de back.verilog: detect undriven public wires using Yosys.
This should never happen, and is certainly a logic bug in nMigen.
2018-12-13 04:59:48 +00:00
whitequark 4d3258013d Initial commit. 2018-12-12 03:18:44 +00:00