whitequark
06faeee357
back.verilog: better error message if Yosys is not found.
...
Fixes #17 .
2019-01-13 08:10:23 +00:00
whitequark
307de722cb
back.verilog: remove undriven check.
...
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.
Fixes #23 .
2019-01-08 22:43:09 +00:00
whitequark
6ee80408bb
back.verilog: do not rename internal signals.
...
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
2018-12-22 00:53:40 +00:00
whitequark
a061bfaa6c
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
2018-12-21 04:22:16 +00:00
whitequark
2b4a8510ca
back.rtlil: implement memories.
2018-12-21 01:55:59 +00:00
whitequark
ac498414ab
back.verilog: remove debug code.
2018-12-13 13:42:54 +00:00
whitequark
6251c95d4e
compat.genlib.fsm: import/wrap Migen code.
2018-12-13 12:41:19 +00:00
whitequark
4e32f6b8de
back.verilog: detect undriven public wires using Yosys.
...
This should never happen, and is certainly a logic bug in nMigen.
2018-12-13 04:59:48 +00:00
whitequark
4d3258013d
Initial commit.
2018-12-12 03:18:44 +00:00
