whitequark
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9ba2efd86b
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build.{res,plat}: use xdr=0 as default, not xdr=1.
The previous behavior was semantically incorrect.
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2019-06-03 03:36:32 +00:00 |
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whitequark
|
3327deae92
|
vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.
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2019-06-03 03:01:56 +00:00 |
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whitequark
|
dc17d06fe9
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vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
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2019-06-03 02:51:59 +00:00 |
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whitequark
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98497b2075
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build.dsl: require a dict for extras instead of a stringly array.
Fixes #72.
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2019-06-02 23:36:21 +00:00 |
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whitequark
|
e4ebe03115
|
vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles.
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2019-06-02 04:12:50 +00:00 |
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|
whitequark
|
37152c733e
|
vendor.tinyfpga_{b→bx}
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2019-06-02 04:11:28 +00:00 |
|
|
whitequark
|
bff08c5016
|
vendor.tinyfpga_b: fix IO_STANDARD.
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2019-06-02 04:04:07 +00:00 |
|
|
Simon Kirkby
|
358b98e5de
|
vendor.tinyfpga_b: implement.
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2019-06-02 01:20:09 +00:00 |
|
|
whitequark
|
39fad9a955
|
vendor.icestick: fix typo.
|
2019-06-02 01:13:03 +00:00 |
|
|
whitequark
|
ba0fcddb2c
|
vendor.ice40_hx1k_blink_evn: implement.
|
2019-06-01 16:48:07 +00:00 |
|
|
whitequark
|
eab372383a
|
vendor.icestick: implement.
|
2019-06-01 16:47:20 +00:00 |
|
|
whitequark
|
321d245e95
|
vendor.fpga.lattice_ice40: implement.
|
2019-06-01 16:47:01 +00:00 |
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