Current the value compiler translates ArrayProxy into if-elif trees
which can cause the compiler to crash due to deep recursion (#359).
After this commit, it instead translates them into pattern matching
when it is supported (on Python >= 3.10) to avoid this problem.
Formatting large ints to decimal raises an ValueError in Python versions
that include a mitigation for CVE-2020-10735. Formatting to hexadecimal
instead avoids the algorithmic complexity and is not impacted by the
new conversion limits.
Note that the simulator already rejects very large values, but the
integer-string conversion limits trigger in cases that previously
worked.
These operators are ignored when they are encountered on LHS, as
the signedness of the assignment target does not matter in Amaranth.
.as_signed() appears on LHS of assigns to signed aggregate fields.
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.
Fixes#535.
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.
This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.
Fixes#588.
