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Author SHA1 Message Date
whitequark ab5426ce74 Improve test added in 29fee01f to not leak warnings. 2019-08-03 13:44:44 +00:00
whitequark ee03eab52f back.rtlil: fix sim-synth mismatch with assigns following switches. 
Closes #155.
 2019-08-03 13:27:47 +00:00
whitequark 0a603b3844 hdl.ast: fix typo. 2019-08-03 13:21:09 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. 
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
 2019-08-03 12:51:57 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00
whitequark 995e4adb8c hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. 
Fixes #154.
 2019-07-31 05:20:05 +00:00
N. Engelhardt 5fd8a796ae vendor: don't emit duplicate iobuf submodule names. 
These are no longer allowed after commit 698b005.
 2019-07-21 07:49:21 +00:00
N. Engelhardt 698b005182 hdl.dsl: add getters to m.submodules. 2019-07-19 12:39:47 +00:00
Alain Péteut 81e59832fb lib.fifo: fix typo. 2019-07-15 14:12:33 +00:00
Staf Verhaegen ff343d5cf0 Pin: Add extra hierarchy level for name derivation 2019-07-14 19:30:12 +00:00
William D. Jones b963449b41 build.run: Ensure batch script returns proper error code. 2019-07-14 17:43:33 +00:00
whitequark ee15538cf0 back.pysim: correctly add gtkwave traces for signals with decoders. 2019-07-12 13:35:44 +00:00
William D. Jones 6ee760e83f build.dsl: Add optional name_suffix to Resource.family. 2019-07-10 15:41:23 +00:00
whitequark 278b624c66 back.pysim: avoid malformed VCD files when a decoder uses tabs. 2019-07-10 12:54:59 +00:00
whitequark 2fa858b003 hdl.ir: make UnusedElaboratable a real warning. 
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
 2019-07-10 12:46:54 +00:00
whitequark 37f363e338 back.rtlil: add decodings to cases when switching on a signal. 
Fixes #134.
 2019-07-09 19:48:15 +00:00
whitequark 10e56c75fb back.verilog: run proc_prune for much cleaner output. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@44bcb7a1.
 2019-07-09 19:28:09 +00:00
whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
 2019-07-09 19:26:47 +00:00
Jacob Lifshay 62b3e36612 tracer: add PyPy support to get_var_name(). 
Fixes #141.
 2019-07-09 07:29:01 +00:00
whitequark 367ad5aee7 build.dsl: add Resource.family abstraction. 2019-07-09 02:44:03 +00:00
whitequark 7b4fbf8e01 build.{dsl,res}: allow platform-dependent attributes using callables. 
Fixes #132.
 2019-07-08 11:15:04 +00:00
whitequark 0ab0a74ec1 hdl.rec: respect modifications to signals in Record.like(). 
Fixes #126.
 2019-07-08 10:59:15 +00:00
whitequark bfbeca4584 back.rtlil: don't name-prefix signals connected to instance ports. 
This gives particularly pathological results on IO buffers, like:
  connect \D_OUT_0 \user_led_0_user_led_0__o

Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
 2019-07-08 10:48:07 +00:00
whitequark 0b844da4cf build.{dsl,res}: allow removing attributes from subsignals. 
This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.

Fixes #128.
 2019-07-08 10:42:10 +00:00
whitequark f0c1c2cfeb build.dsl: allow assertions on subsignal widths. 
This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.
 2019-07-08 10:42:06 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark 345a26b04b test: fix Travis. 2019-07-08 10:22:47 +00:00
whitequark 5c63177fc2 test: generate examples to verilog as part of unit tests. 
This is to make sure 806a62c2 doesn't happen again.
 2019-07-08 10:12:26 +00:00
whitequark c14d074fcc examples/basic/ctr_ce: fix outdated syntax. 2019-07-08 10:12:26 +00:00
whitequark 447bfa6ad5 compat.genlib.fsm: fix after commit dac62754. 2019-07-08 10:12:26 +00:00
whitequark ec7fcd3697 hdl.xfrm: don't overwrite source locations on ClockDomain signals. 
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
 2019-07-08 09:58:12 +00:00
whitequark 8c9fdf907f hdl.{dsl,mem,xfrm}: inject appropriate source locations. 
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.

On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
 2019-07-08 09:58:12 +00:00
whitequark 710a8d0bc1 back.rtlil: ignore empty source locations. 
This was a bug introduced during refactoring in 2492f490.
 2019-07-08 09:58:12 +00:00
whitequark dac6275493 hdl.ast: use keyword-only arguments as appropriate. 
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
 2019-07-08 09:58:12 +00:00
whitequark 70f3563b5f back.rtlil: attach source locations to switches, not processes. 
This effectively reverts and reimplements half of commit 82903e49.
I was confused and did not realize that RTLIL does, in fact, have
attributes on switches.

After this commit, processes no longer have any source locations.
This is semantically fine, as the processes we emit are purely
artificial (because of LHS grouping), but I have not checked how
downstream tooling handles this.
 2019-07-08 09:10:09 +00:00
whitequark 2492f490f5 back.rtlil: use a more principled approach to attributes. NFC. 
This also refactors the RTLIL builder to use a more aspect-oriented
approach.
 2019-07-08 09:10:09 +00:00
Alain Péteut 31c54d32ef vendor.xilinx_7series: generate also binary bitfile. 
Fixes #139.
 2019-07-07 21:36:32 +00:00
William D. Jones b404d603fb vendor.xilinx_spartan_3_6: Add Spartan3A family support. 2019-07-07 20:44:48 +00:00
whitequark cb02a452e9 vendor.lattice_ecp5: don't leave LUT inputs disconnected. 
This causes YosysHQ/nextpnr#301.

Fixes #136.
 2019-07-07 02:34:22 +00:00
whitequark da1f58b7ae hdl.dsl: further clarify error message for incorrect nesting. 
Fixes #133.
 2019-07-07 01:03:59 +00:00
whitequark cb8be4a1b0 hdl.dsl: clarify error message for incorrect nesting. 
Refs #133.
 2019-07-07 00:59:57 +00:00
whitequark 3388b5b085 hdl.dsl: gracefully handle FSM with no states. 2019-07-07 00:59:34 +00:00
whitequark 146f3cb684 build.plat: source a script with toolchain environment. 
Fixes #131.
 2019-07-07 00:44:28 +00:00
whitequark 744154ebb5 build.run: only use os.path on the target OS. 
Before this commit, BuildPlan.add_file would use os.path.normpath,
which would be the wrong thing for cross-builds.
 2019-07-07 00:18:56 +00:00
whitequark ba64eb2037 build.run: make BuildProducts abstract, add LocalBuildProducts. 
This makes it clear that we plan to have remote builds as well.

Also, document everything in build.run.
 2019-07-07 00:09:07 +00:00
whitequark 1ee21d2007 build.plat, vendor.*: don't join strings passed as _opts overrides. 
Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.

Fixes #130.
 2019-07-06 23:09:46 +00:00
whitequark b6b9f0fc21 build.run: make sure BuildProducts._root is not easily accessible. 2019-07-06 18:52:48 +00:00
Staf Verhaegen 2829d04033 vendor.xilinx_{7series,spartan6}: Support extra VHDL files. 2019-07-04 21:13:33 +00:00
whitequark 2e4cc47fcb hdl.dsl: fix src_loc_at for FSM state signal. 2019-07-03 16:34:31 +00:00