whitequark
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c98b8f7c07
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compat.fhdl.specials: fix Memory.get_port() after 94e8f479.
This also makes sure the native ports are instantiated for correct
clock domain.
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2019-07-03 13:24:00 +00:00 |
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whitequark
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38917e4523
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compat.fhdl.specials: fix platform lowering for TSTriple again.
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2019-06-04 13:03:56 +00:00 |
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whitequark
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79a3710255
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compat.fhdl.specials: fix platform lowering.
get_tristate only has O/OE; the triple is created by get_input_output.
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2019-06-04 12:26:09 +00:00 |
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whitequark
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4c443a7ef5
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compat.fhdl.specials: TSTriple is not an elaboratable.
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2019-06-03 09:39:38 +00:00 |
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Chris Osterwood
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699fe5a675
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Add import so that Tristate.elaborate builds
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2019-05-20 16:34:31 +00:00 |
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Alain Péteut
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c8e92c0612
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compat.fhdl.specials: fix Tristate, TSTriple.
* fix TSTriple instance.
* TSTriple, Tristate: tag as Elaboratable
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2019-04-22 09:57:12 +00:00 |
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|
Alain Péteut
|
371dc8bebe
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compat.fhdl.specials: fix Tristate.
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2019-04-22 08:49:08 +00:00 |
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|
whitequark
|
93d15abcf1
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compat.fhdl.specials: fix TSTriple.
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2019-04-22 08:15:03 +00:00 |
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|
whitequark
|
287a0531b3
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lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin.
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2019-04-15 16:27:23 +00:00 |
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whitequark
|
ce7ba70462
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compat.fhdl.specials: fix __all__ list.
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2019-01-26 22:59:33 +00:00 |
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whitequark
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4948162f33
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hdl.ir: rename .get_fragment() to .elaborate().
Closes #9.
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2019-01-26 02:31:12 +00:00 |
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whitequark
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e3b5b2acc8
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fhdl.specials: add compatibility shim for Tristate.
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2019-01-19 02:20:40 +00:00 |
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|
whitequark
|
5361b4c22b
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compat: fix confusing naming for memory port address signal.
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2018-12-22 00:53:05 +00:00 |
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whitequark
|
568d3c5b7d
|
compat: provide Memory shim.
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2018-12-21 13:15:52 +00:00 |
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|
whitequark
|
790eb05a92
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Rename fhdl→hdl, genlib→lib.
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2018-12-15 14:25:31 +00:00 |
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|
whitequark
|
ecea721f43
|
compat.fhdl.module: allow adding native submodules to compat modules.
|
2018-12-14 23:56:50 +00:00 |
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|
whitequark
|
3b23645fb7
|
compat: add fhdl.specials.TSTriple shim.
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2018-12-14 16:09:51 +00:00 |
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