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Author SHA1 Message Date
whitequark 921f506e69 back.rtlil: assign undriven signals to their reset value. 
Fixes #35.
 2019-05-13 08:33:55 +00:00
whitequark 744e33f42d hdl: make all public Value classes other than Record final. 
In some cases, nMigen uses type() instead of isinstance() to dispatch
on types. Make sure all such uses of type() are robust; in addition,
make it clear that nMigen AST classes are not meant to be subclassed.
(Record is an exception.)

Fixes #65.
 2019-05-12 05:40:17 +00:00
whitequark 958cb18b88 hdl.ir: only pull explicitly specified ports to toplevel, if any. 
Fixes #30.
 2019-05-12 05:21:23 +00:00
Jean-François Nguyen 6a77122c2e lib.io: add a name argument to the Pin constructor. 2019-04-24 22:02:20 +00:00
whitequark a982fbe377 build.dsl: style. NFC. 2019-04-24 15:02:30 +00:00
Jean-François Nguyen dd5bd1c88d build: add DSL for defining platform resources. 2019-04-24 11:49:01 +00:00
whitequark 97af266645 back.verilog: allow stripping the src attribute, for cleaner output. 2019-04-22 14:59:53 +00:00
Alain Péteut c8e92c0612 compat.fhdl.specials: fix Tristate, TSTriple. 
* fix TSTriple instance.
* TSTriple, Tristate: tag as Elaboratable
 2019-04-22 09:57:12 +00:00
Alain Péteut 371dc8bebe compat.fhdl.specials: fix Tristate. 2019-04-22 08:49:08 +00:00
whitequark 93d15abcf1 compat.fhdl.specials: fix TSTriple. 2019-04-22 08:15:03 +00:00
whitequark 585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark aed2062101 Remove examples/tbuf.py. 
This example predates the plans for nmigen.build, and indeed
get_tristate and TSTriple no longer exist.
 2019-04-21 08:53:37 +00:00
whitequark 44711b7d08 hdl.ir: detect elaboratables that are created but not used. 
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
 2019-04-21 08:52:57 +00:00
whitequark 85ae99c1b4 back.rtlil: emit nmigen.hierarchy attribute. 
Fixes #54.
 2019-04-21 07:55:08 +00:00
whitequark 360bc9b5b4 hdl.ast: improve tests for exceptional conditions. 2019-04-21 07:20:00 +00:00
whitequark 33f9bd2a1d hdl.ast: accept Signals with identical min/max bounds. 
And produce a 0-bit signal.

Fixes #58.
 2019-04-21 07:16:59 +00:00
whitequark 083016d747 back.rtlil: only expand legalized values in Array/Part context on RHS. 
Otherwise the following code fails to compile:

    index = Signal(1)
    array = Array(range(2))
    with m.If(0 == array[index]):
        m.d.sync += index.eq(0)

Fixes #51.
 2019-04-21 06:43:31 +00:00
whitequark ce1eff5464 hdl.rec: implement Record.connect. 
Fixes #31.
 2019-04-21 06:37:08 +00:00
whitequark f22106e5ef back.rtlil: allow record slices on LHS. 2019-04-20 08:12:29 +00:00
whitequark 611c25f909 hdl.rec: fix slicing of records. 2019-04-19 19:55:39 +00:00
whitequark dda8f34d39 hdl.xfrm: handle classes that inherit from Record. 2019-04-18 17:06:33 +00:00
whitequark 287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
whitequark 50fa2516fa hdl.ast: fix some type checks. 2019-04-10 04:33:44 +00:00
whitequark 0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. 
Fixes #29.
 2019-04-10 00:23:11 +00:00
whitequark 49eef77c53 hdl: remove deprecated get_fragment() and lower() methods. 2019-04-09 23:53:43 +00:00
whitequark a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). 2019-04-03 14:59:01 +00:00
whitequark c9c9307a5e test_sim: add missing add_process(). 
Fixes #43.
 2019-03-28 17:50:14 +00:00
Luke Wren 23a07b955f lib.cdc: add optional reset to MultiReg, and document its use cases. 2019-03-28 05:21:48 +00:00
whitequark a57c72d606 back.rtlil: fix off-by-one in Part legalization. 
Fixes #52.
 2019-03-28 05:12:12 +00:00
anuejn 3c95299c4e hdl.rec: separate record and signal name with __, not _. 
This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
 2019-03-25 14:26:00 +00:00
whitequark 81ee2db163 hdl.ast: fix typo. 
Fixes #49.
 2019-03-25 10:50:39 +00:00
Alain Péteut d69a4e29a8 examples.por: fix typo 2019-03-12 02:14:21 +00:00
whitequark 4027317835 lib.fifo: register GrayEncoder output before CDC. 
Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.

Reported by @Wren6991.
 2019-03-03 18:23:51 +00:00
whitequark e93bf4bf4b tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00
whitequark cac4b10b82 hdl.rec: remove __slots__. 
Left in by mistake.
 2019-03-03 18:21:22 +00:00
Alain Péteut 342bdbe75a setup.py: constrain Python version 
Installation should be constraint to supported Python versions, using `python_requires`,
refer to [1] for details.

[1] https://packaging.python.org/guides/distributing-packages-using-setuptools/#python-requires
 2019-02-22 08:45:28 +00:00
whitequark 8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark 43e4833ddb back.rtlil: accept ast.Const as cell parameter. 2019-01-26 23:25:54 +00:00
whitequark bc5a127fd2 hdl.ast: fix ValueKey for Cat. 2019-01-26 23:25:34 +00:00
whitequark e844b0e095 compat.fhdl.module: fix typo. 2019-01-26 23:08:55 +00:00
whitequark ce7ba70462 compat.fhdl.specials: fix __all__ list. 2019-01-26 22:59:33 +00:00
whitequark 6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer. 2019-01-26 18:24:36 +00:00
whitequark 2fb85a6170 compat.fifo: fix _FIFOInterface deprecation wrapper. 2019-01-26 18:23:58 +00:00
whitequark f44ca291c1 lib.cdc: add ResetSynchronizer. 2019-01-26 18:07:59 +00:00
whitequark e74dbc3377 back.pysim: support async reset. 2019-01-26 18:07:43 +00:00
whitequark 8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. 
Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)
 2019-01-26 18:07:16 +00:00
whitequark 7acea8f3ce examples: update for newer API. 2019-01-26 16:25:05 +00:00
whitequark b133eb735f back.rtlil: accept any elaboratable, not just fragments. 2019-01-26 16:11:29 +00:00
whitequark 4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
whitequark 7890c0adc8 test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00