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Author SHA1 Message Date
whitequark db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics. 
This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
 2019-10-11 11:47:42 +00:00
whitequark fa1e466a65 hdl.ast: Operator.{op→operator} 
Both "operator" and "operand" were shortened to "op" in different
places in code, which caused confusion.
 2019-10-11 11:37:26 +00:00
whitequark 7ff4c6ce43 hdl.ast: simplify enum handling. 2019-10-11 11:16:00 +00:00
whitequark d72d4a55fd hdl.ast: Value.{wrap→cast} 
Preparation for #225.
 2019-10-11 10:49:34 +00:00
whitequark de34728bf8 hdl.ast: prohibit signed divisors. 
See #238.
 2019-10-04 07:49:24 +00:00
whitequark 9458de2079 hdl.ast: don't crash on Mux(<bool>, ...). 
Fixes #240.
 2019-10-02 08:30:15 +00:00
whitequark 1621ceb65a hdl.ast: actually implement the // operator. 2019-09-28 19:33:24 +00:00
whitequark b227352258 hdl.ast: cast Mux() selector to bool if it is not a 1-bit value. 
Fixes #232.
 2019-09-23 13:39:31 +00:00
whitequark 649444449d hdl.ast: make Signal(name=) a keyword-only argument. 
Almost no code would specify Signal(_, name) as a positional argument
on purpose, but forgetting parens and accidentally placing signedness
into the name position is so common that we had a test for it.
 2019-09-23 11:08:43 +00:00
whitequark a13a21cbd6 hdl.ast: update docs. NFC. 2019-09-21 06:53:13 +00:00
whitequark 378e924280 hdl.ast: rename nbits to width. 
Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.

This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)

Fixes #210.
 2019-09-20 15:36:25 +00:00
whitequark 4777a7b3a2 hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns. 
Fixes #207.
 2019-09-16 19:22:12 +00:00
whitequark e8f79c5539 hdl.ast: add Value.matches(), accepting same language as Case(). 
Fixes #202.
 2019-09-14 21:06:12 +00:00
whitequark 32310aecad hdl.ast: add Value.xor, mapping to $reduce_xor. 
Fixes #147.
 2019-09-13 14:29:46 +00:00
whitequark b23a9794a4 hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}. 
Refs #147.
 2019-09-13 13:14:52 +00:00
whitequark 7342662bee hdl.ast: warn if reset value is truncated. 
Fixes #183.
 2019-09-10 07:26:34 +00:00
whitequark 9b398b502e hdl.ast: check type of Sample(domain=...). 
Fixes #199.
 2019-09-08 23:55:05 +00:00
whitequark ccfbccc044 hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...). 
Fixes #196.
 2019-09-08 12:10:31 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover. 
Fixes #194.
 2019-09-03 01:32:24 +00:00
whitequark 32bfbb11cb formal→asserts 
Closes #171.
 2019-08-19 20:23:24 +00:00
whitequark ed7e07c6c1 hdl.ast: implement Initial. 
This is the last remaining part for first-class formal support.
 2019-08-15 02:53:07 +00:00
whitequark 9d2cbbabb8 hdl.ast: hash-cons ValueKey. 
This speeds up elaboration by ~10%.
 2019-08-08 10:56:53 +00:00
whitequark 0a603b3844 hdl.ast: fix typo. 2019-08-03 13:21:09 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. 
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
 2019-08-03 12:51:57 +00:00
whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
 2019-07-09 19:26:47 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark 8c9fdf907f hdl.{dsl,mem,xfrm}: inject appropriate source locations. 
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.

On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
 2019-07-08 09:58:12 +00:00
whitequark dac6275493 hdl.ast: use keyword-only arguments as appropriate. 
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
 2019-07-08 09:58:12 +00:00
whitequark 82903e493a back.rtlil: emit \src attributes for processes via Switch and Assign. 
The locations are unfortunately not very precise, but they provide
some improvement over status quo.
 2019-07-03 16:27:54 +00:00
whitequark e351e27206 hdl.ast: fix src_loc_at for Mux(). 2019-07-03 15:25:14 +00:00
whitequark 0ab215e5ed hdl.ast: recognize a Enum used as decoder and format it better. 2019-07-02 19:34:44 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. 
This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
 2019-06-25 22:01:14 +00:00
whitequark f1174655b1 hdl.ast: tighten assertion in Switch(). 2019-06-13 03:56:57 +00:00
whitequark e52b15d236 hdl.ast: add name_suffix=".." option to Signal.like(). 
This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff
 2019-06-12 22:26:57 +00:00
whitequark ad1a40c934 hdl.ast: implement values with custom lowering. 2019-06-11 07:01:44 +00:00
whitequark 744e33f42d hdl: make all public Value classes other than Record final. 
In some cases, nMigen uses type() instead of isinstance() to dispatch
on types. Make sure all such uses of type() are robust; in addition,
make it clear that nMigen AST classes are not meant to be subclassed.
(Record is an exception.)

Fixes #65.
 2019-05-12 05:40:17 +00:00
whitequark 33f9bd2a1d hdl.ast: accept Signals with identical min/max bounds. 
And produce a 0-bit signal.

Fixes #58.
 2019-04-21 07:16:59 +00:00
whitequark 50fa2516fa hdl.ast: fix some type checks. 2019-04-10 04:33:44 +00:00
whitequark a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). 2019-04-03 14:59:01 +00:00
whitequark 81ee2db163 hdl.ast: fix typo. 
Fixes #49.
 2019-03-25 10:50:39 +00:00
whitequark e93bf4bf4b tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00
whitequark bc5a127fd2 hdl.ast: fix ValueKey for Cat. 2019-01-26 23:25:34 +00:00
whitequark f71e0fffbb hdl.ast: fix shape calculation for *. 
This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
 2019-01-26 00:56:40 +00:00
whitequark 38b3c4af31 hdl.ast: implement shape for modulo operator. 2019-01-19 09:27:56 +00:00
whitequark 5e2b46f727 hdl.ast: add Value.implies. 2019-01-19 08:56:44 +00:00
whitequark b50b47d984 hdl.ast: give Assert and Assume their own src_loc. 
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
 2019-01-19 00:08:51 +00:00
whitequark 66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. 
These are semantically like signals, not like constants.
 2019-01-18 01:34:48 +00:00
whitequark fa8e876356 hdl.ast: allow sampling ClockSignal, ResetSignal. 2019-01-17 05:23:06 +00:00