whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
4199674edd
back.pysim: implement *.
2018-12-18 18:02:21 +00:00
whitequark
07e9cfa939
test.sim: add tests for sync functionality and errors.
2018-12-18 17:53:50 +00:00
whitequark
7fa82a70be
back.pysim: eliminate most dictionary lookups.
...
This makes the Glasgow testsuite about 30% faster.
2018-12-18 16:36:54 +00:00
whitequark
7341d0d7ef
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
2018-12-18 16:13:29 +00:00
whitequark
c5f169988b
back.pysim: use arrays instead of dicts for signal values.
...
This makes the Glasgow testsuite about 40% faster.
2018-12-18 05:20:20 +00:00
whitequark
39605ef551
back.pysim: naming. NFC.
2018-12-18 04:46:36 +00:00
whitequark
65702719e8
back.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 04:43:04 +00:00
whitequark
34b81d0b87
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
2018-12-18 04:37:39 +00:00
whitequark
d6e98fd934
back.pysim: continue running simulator processes until they suspend.
2018-12-18 03:05:16 +00:00
whitequark
51a92bc870
Travis: cache Yosys installation explicitly.
2018-12-18 00:42:14 +00:00
whitequark
c7f9386eab
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
2018-12-17 22:55:39 +00:00
whitequark
de6c12af77
Travis: build and cache Yosys.
2018-12-17 17:21:42 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
8c4de99c0d
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
2018-12-17 17:21:29 +00:00
whitequark
f1e390cbc9
back.rtlil: update for Yosys master.
2018-12-17 15:50:43 +00:00
whitequark
850674637a
back.rtlil: implement Array.
2018-12-17 01:15:23 +00:00
whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
f968678937
back.rtlil: handle reset_less domains.
2018-12-16 23:52:47 +00:00
whitequark
015998eba9
hdl.dsl: add clock domain support.
2018-12-16 23:51:24 +00:00
whitequark
b2f828387a
hdl.dsl: cleanup. NFC.
2018-12-16 23:44:00 +00:00
whitequark
91b7561a00
back.rtlil: extract _StatementCompiler. NFC.
2018-12-16 22:26:58 +00:00
whitequark
b9a0af8bde
back.rtlil: simplify. NFC.
2018-12-16 21:00:00 +00:00
whitequark
635094350f
back.rtlil: properly escape strings in attributes.
2018-12-16 20:27:36 +00:00
whitequark
41d69c3ad7
README: mention Yosys requirement.
2018-12-16 18:09:11 +00:00
whitequark
33f32a25f5
back.rtlil: prepare for Yosys sigspec slicing improvements.
...
See YosysHQ/yosys#741 .
2018-12-16 18:03:14 +00:00
whitequark
db5fd1e4c4
compat.fhdl.structure: only convert to bool in If/Elif if necessary.
2018-12-16 17:41:42 +00:00
whitequark
9bce35098f
back.rtlil: avoid illegal slices.
...
Not sure what to do with {} [] on LHS yet--fix Yosys?
2018-12-16 17:41:11 +00:00
whitequark
e86104d3a6
back.rtlil: use slicing to match shape when reducing width.
2018-12-16 16:20:45 +00:00
whitequark
2833b36c73
back.rtlil: don't emit a slice if all bits are used.
2018-12-16 16:05:38 +00:00
whitequark
9794e732e2
back.rtlil: reorganize value compiler into LHS/RHS.
...
This also implements Cat on LHS.
2018-12-16 13:33:34 +00:00
whitequark
ed39748889
back.rtlil: fix naming. NFC.
2018-12-16 11:26:31 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
286a8009c8
compat.fhdl: reexport Array.
2018-12-16 10:39:54 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
d9579219ee
test.sim: generalize assertOperator. NFC.
2018-12-15 21:08:29 +00:00
whitequark
bdb8db2826
back.pysim: add (stub) LHSValueCompiler.
2018-12-15 21:01:38 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
1adf58f561
examples: rename clkdiv/ctrl to ctr/ctr_ce.
2018-12-15 20:42:52 +00:00
whitequark
6c601fecfa
doc: update COMPAT_SUMMARY.
2018-12-15 20:40:56 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
80c5343600
hdl.ast: implement Array and ArrayProxy.
2018-12-15 17:16:31 +00:00
whitequark
1580b6e542
Lower Python version requirement to 3.6.
2018-12-15 17:03:23 +00:00
whitequark
c6e7a93717
hdl: appropriately rename tests. NFC.
2018-12-15 16:13:53 +00:00
whitequark
f603b735e8
hdl.ast: improve ClockSignal, ResetSignal documentation.
2018-12-15 14:58:31 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
b5a1efa0c8
Move star imports to make from nmigen import * usable.
2018-12-15 14:20:10 +00:00
whitequark
ad3c88852f
doc: fix some Markdown awkwardness.
2018-12-15 12:07:56 +00:00
whitequark
cc96a7ecfa
doc: update COMPAT_SUMMARY to reflect actual status.
2018-12-15 12:04:52 +00:00
whitequark
1f10bd96b9
Determine Migen's API surface and document compatibility summary.
...
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
2018-12-15 11:52:30 +00:00
