whitequark
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fa8e876356
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hdl.ast: allow sampling ClockSignal, ResetSignal.
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2019-01-17 05:23:06 +00:00 |
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whitequark
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8c96675580
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hdl.ast: add Past, Stable, Rose, Fell.
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2019-01-17 04:31:27 +00:00 |
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whitequark
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198efcad31
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hdl.xfrm: add SampleLowerer.
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2019-01-17 01:41:02 +00:00 |
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whitequark
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b3de114d67
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hdl.ast: add Sample.
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2019-01-17 01:36:27 +00:00 |
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whitequark
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b78a2be9f6
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lib.fifo: port sync FIFO queues from Migen.
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2019-01-16 17:20:38 +00:00 |
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whitequark
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cb2f18ee37
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hdl.ast: fix naming of Signal.like() signals when tracer fails.
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2019-01-16 17:20:38 +00:00 |
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whitequark
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b534e92dd5
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hdl.ir: allow explicitly requesting flattening.
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2019-01-14 17:04:23 +00:00 |
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whitequark
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011bf2258e
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hdl: make ClockSignal and ResetSignal usable on LHS.
Fixes #8.
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2019-01-14 15:38:16 +00:00 |
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whitequark
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664b4bcb3a
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hdl.dsl: cases wider than switch test value are unreachable.
In 3083c1d6 they were erroneously fixed via truncation.
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2019-01-13 08:51:49 +00:00 |
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whitequark
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3083c1d6dd
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hdl.dsl: accept (but warn on) cases wider than switch test value.
Fixes #13.
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2019-01-13 08:46:28 +00:00 |
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whitequark
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cbf7bd6e31
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back.pysim: handle non-driven, non-port signals.
Fixes #20.
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2019-01-13 08:31:38 +00:00 |
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William D. Jones
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2412650f56
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hdl.dsl: Support Assert and Assume where an Assign can occur.
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2019-01-02 11:17:39 +00:00 |
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whitequark
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3c07d8d52c
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hdl.rec: include record name in error message.
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2019-01-01 03:39:12 +00:00 |
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whitequark
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031a9e2616
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hdl.rec: use a helpful error on unknown field reference.
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2019-01-01 03:35:34 +00:00 |
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whitequark
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d78e6c155b
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hdl.mem: add DummyPort, for testing and verification.
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2019-01-01 03:08:10 +00:00 |
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whitequark
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39eb2e8fa7
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lib.cdc: fix tests to actually run.
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2018-12-29 15:02:44 +00:00 |
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whitequark
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849c649259
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back.pysim: warn if simulation is not run.
This would have prevented 3ea35b85.
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2018-12-29 15:02:04 +00:00 |
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whitequark
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92a96e1644
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hdl.rec: add basic record support.
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2018-12-28 13:22:10 +00:00 |
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whitequark
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3ea35b8566
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lib.coding: fix tests to actually run, and fix code to fix tests.
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2018-12-27 21:45:55 +00:00 |
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whitequark
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470d66934f
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hdl.dsl: add support for fsm.ongoing().
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2018-12-27 16:19:01 +00:00 |
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whitequark
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528747703d
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lib.coding: port from Migen.
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2018-12-26 13:19:34 +00:00 |
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whitequark
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fe8cb55204
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lib.cdc: add tests for MultiReg.
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2018-12-26 12:58:30 +00:00 |
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whitequark
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35a44f017f
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hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
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2018-12-26 12:42:43 +00:00 |
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whitequark
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934546e633
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hdl.dsl: provide generated values for FSMs.
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2018-12-26 12:39:05 +00:00 |
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whitequark
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040811c2e5
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hdl.ir: add an API for retrieving generated values, like FSM signal.
This is useful for tests.
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2018-12-26 12:35:35 +00:00 |
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whitequark
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54e3195dcb
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hdl.dsl: implement FSM.
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2018-12-26 08:55:04 +00:00 |
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whitequark
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98f554aa08
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hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
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2018-12-24 02:17:28 +00:00 |
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whitequark
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1c7c75a254
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hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
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2018-12-24 02:02:59 +00:00 |
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whitequark
|
621dddebfd
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hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
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2018-12-22 22:19:14 +00:00 |
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whitequark
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68dae9f50e
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hdl.ir: flatten hierarchy based on memory accesses, too.
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2018-12-22 21:43:46 +00:00 |
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whitequark
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ae0cb48fbb
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hdl.xfrm: implement LHSGroupAnalyzer.
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2018-12-22 06:58:24 +00:00 |
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whitequark
|
f6772759c8
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hdl.ir: fix port propagation between siblings, in the other direction.
|
2018-12-22 00:31:31 +00:00 |
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whitequark
|
913339c04a
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hdl.ir: fix port propagation between siblings.
|
2018-12-21 23:53:18 +00:00 |
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whitequark
|
fa2af27bb0
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hdl.mem: ensure transparent read port model has correct latency.
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2018-12-21 13:01:08 +00:00 |
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whitequark
|
48d13e47ec
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back.pysim: handle out of bounds ArrayProxy indexes.
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2018-12-21 12:32:08 +00:00 |
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whitequark
|
e58d9ec74d
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hdl.mem: add simulation model for memory.
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2018-12-21 11:54:32 +00:00 |
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whitequark
|
c49211c76a
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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whitequark
|
b0bd7bfaca
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hdl.ir: correctly handle named output and inout ports.
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2018-12-21 04:03:03 +00:00 |
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whitequark
|
f7fec804ec
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ir: allow non-Signals in Instance ports.
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2018-12-20 23:40:40 +00:00 |
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whitequark
|
dbbcc49a71
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hdl.ast: Cat.{operands→parts}
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2018-12-18 19:15:50 +00:00 |
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whitequark
|
4199674edd
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back.pysim: implement *.
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2018-12-18 18:02:21 +00:00 |
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whitequark
|
07e9cfa939
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test.sim: add tests for sync functionality and errors.
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2018-12-18 17:53:50 +00:00 |
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whitequark
|
c7f9386eab
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fhdl.ir: add black-box fragments, fragment parameters, and Instance.
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2018-12-17 22:55:39 +00:00 |
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whitequark
|
8d1639a5a8
|
hdl, back: add and use SignalSet/SignalDict.
|
2018-12-17 17:21:29 +00:00 |
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|
whitequark
|
015998eba9
|
hdl.dsl: add clock domain support.
|
2018-12-16 23:51:24 +00:00 |
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|
whitequark
|
d4e8d3e95a
|
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
|
2018-12-16 10:31:42 +00:00 |
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whitequark
|
d9579219ee
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test.sim: generalize assertOperator. NFC.
|
2018-12-15 21:08:29 +00:00 |
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whitequark
|
20a04bca88
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back.pysim: implement Part.
|
2018-12-15 20:58:06 +00:00 |
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|
whitequark
|
54fb999c99
|
back.pysim: implement ArrayProxy.
|
2018-12-15 19:37:36 +00:00 |
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|
whitequark
|
80c5343600
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hdl.ast: implement Array and ArrayProxy.
|
2018-12-15 17:16:31 +00:00 |
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