whitequark 066dd799e8 back.pysim: check for a clock being added twice. ... This commit adds a best-effort error for a common mistake of adding a clock driving the same domain twice, such as a result of a copy-paste error. Fixes #27.		2019-06-11 03:54:22 +00:00
..
compat	compat: suppress deprecation warnings that are internal or during test.	2019-01-26 15:43:00 +00:00
__init__.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test_build_dsl.py	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00
test_build_res.py	build.res: allow querying frequency of a previously constrained clock.	2019-06-05 12:51:53 +00:00
test_compat.py	compat.fhdl.module: CompatModule should be elaboratable.	2019-06-04 11:11:31 +00:00
test_hdl_ast.py	hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.	2019-06-04 10:26:01 +00:00
test_hdl_cd.py	hdl.mem: add tests for all error conditions.	2018-12-21 06:07:16 +00:00
test_hdl_dsl.py	hdl.dsl: allow adding submodules with computed name, like with domains.	2019-06-03 02:22:55 +00:00
test_hdl_ir.py	hdl.ir: accept LHS signals like slices as Instance io ports.	2019-06-03 02:39:14 +00:00
test_hdl_mem.py	hdl.mem: coerce memory init values to integers.	2019-06-11 03:38:44 +00:00
test_hdl_rec.py	hdl.rec: unbreak hasattr(rec, ...).	2019-06-03 07:43:31 +00:00
test_hdl_xfrm.py	hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.	2019-06-04 10:26:01 +00:00
test_lib_cdc.py	Clean up imports.	2019-06-04 08:18:50 +00:00
test_lib_coding.py	Clean up imports.	2019-06-04 08:18:50 +00:00
test_lib_fifo.py	Clean up imports.	2019-06-04 08:18:50 +00:00
test_lib_io.py	Clean up imports.	2019-06-04 08:18:50 +00:00
test_sim.py	back.pysim: check for a clock being added twice.	2019-06-11 03:54:22 +00:00
tools.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00