whitequark 066dd799e8 back.pysim: check for a clock being added twice. ... This commit adds a best-effort error for a common mistake of adding a clock driving the same domain twice, such as a result of a copy-paste error. Fixes #27.		2019-06-11 03:54:22 +00:00
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back	back.pysim: check for a clock being added twice.	2019-06-11 03:54:22 +00:00
build	build.dsl: fix precondition check in Pins.	2019-06-06 20:40:49 +00:00
compat	compat.fhdl.module: silence "unused elaboratable" warnings.	2019-06-04 13:09:36 +00:00
hdl	hdl.mem: coerce memory init values to integers.	2019-06-11 03:38:44 +00:00
lib	lib.cdc: fix typo.	2019-06-09 10:24:01 +00:00
test	back.pysim: check for a clock being added twice.	2019-06-11 03:54:22 +00:00
vendor	vendor.xilinx_spartan6: implement.	2019-06-07 08:58:41 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00