Norbert Braun 14a5c42a8b vendor.xilinx_7series: byte swap generated bitstream ... The Zynq driver in the FPGA Manager framework on Linux expects bitstreams that are byte swapped with respect to what the Vivado command `write_bitstream -bin_file` produces. Thus, use the `write_cfgmem` command with appropriate options to generate the bitstream (.bin file). Fixes #519.		2020-11-03 09:39:49 +00:00
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__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.	2020-08-26 03:19:13 +00:00
lattice_ecp5.py	vendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows.	2020-08-29 19:34:57 +00:00
lattice_ice40.py	vendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC instance.	2020-11-02 06:19:47 +00:00
lattice_machxo2.py	sim: split into base, core, and engines.	2020-08-27 11:52:31 +00:00
lattice_machxo_2_3l.py	vendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows.	2020-08-29 19:34:57 +00:00
quicklogic.py	vendor.quicklogic: utilize internal SoC clock in EOS-S3	2020-10-30 18:11:25 +00:00
xilinx_7series.py	vendor.xilinx_7series: byte swap generated bitstream	2020-11-03 09:39:49 +00:00
xilinx_spartan_3_6.py	lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.	2020-08-26 03:19:13 +00:00
xilinx_ultrascale.py	vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate.	2020-08-26 15:45:58 +00:00