whitequark 6bfff25e76 vendor: yosys is not a required tool for proprietary toolchains. ... Since commit b9799b4c, the discovery mechanism for the Yosys required to produce Verilog is different from the usual require_tool(); namely it is possible to produce Verilog without a `yosys` binary on PATH. Fixes #419.		2020-07-02 18:13:54 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	vendor.intel: don't use write_verilog -decimal.	2020-05-21 09:49:42 +00:00
lattice_ecp5.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
lattice_ice40.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
lattice_machxo2.py	vendor.lattice_machxo2: add back as a compatibility shim.	2020-06-21 17:28:01 +00:00
lattice_machxo_2_3l.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
xilinx_7series.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
xilinx_spartan_3_6.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
xilinx_ultrascale.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00