whitequark 2168ff512b back.verilog: bump Yosys version requirement to 0.9. ... Fixes #55.		2019-08-26 09:59:40 +00:00
..
back	back.verilog: bump Yosys version requirement to 0.9.	2019-08-26 09:59:40 +00:00
build	build.run: add BuildPlan.digest(), useful for caching.	2019-08-23 01:10:51 +00:00
compat	back.{rtlil,verilog}: split convert_fragment() off convert().	2019-08-19 19:49:51 +00:00
hdl	build.plat, hdl.ir: coordinate missing domain creation.	2019-08-19 22:52:01 +00:00
lib	lib.cdc: use a local clock domain in ResetSynchronizer.	2019-08-19 21:45:08 +00:00
test	back.pysim: implement sim.add_clock(if_exists=True).	2019-08-23 08:53:48 +00:00
vendor	vendor.lattice_ecp5: revert default toolchain to Trellis.	2019-08-25 08:07:00 +00:00
__init__.py	Fix nmigen.__version__ to work on git-archive artifacts.	2019-08-19 23:14:41 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
asserts.py	formal→asserts	2019-08-19 20:23:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00