whitequark 45a474788c back.rtlil: only translate switch tests once. ... This seems to affect synthesis with Yosys but only marginally. It is mostly a speed and readability improvement.		2018-12-23 07:17:52 +00:00
..
back	back.rtlil: only translate switch tests once.	2018-12-23 07:17:52 +00:00
compat	compat.genlib.fsm: fix naming for non-Signal LHS.	2018-12-22 22:00:58 +00:00
hdl	hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.	2018-12-22 22:19:14 +00:00
lib	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
test	hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.	2018-12-22 22:19:14 +00:00
__init__.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
cli.py	cli: generate: guess file type from extension.	2018-12-23 07:13:17 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00