whitequark 45a474788c back.rtlil: only translate switch tests once. ... This seems to affect synthesis with Yosys but only marginally. It is mostly a speed and readability improvement.		2018-12-23 07:17:52 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.xfrm: Abstract*Transformer→*Visitor	2018-12-22 06:03:39 +00:00
rtlil.py	back.rtlil: only translate switch tests once.	2018-12-23 07:17:52 +00:00
verilog.py	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00