whitequark 5c626e33bf compat.fhdl.module: fix finalization of transformed compat submodules. ... Before this commit, the TransformedElaboratable of a CompatModule would be ignored, and .get_fragment() would be used to retrieve the CompatModule within. After this commit, the finalization process is reworked to match oMigen's finalization closely, and all submodules, native and compat, are added in the same way that preserves applied transforms.		2019-08-08 07:45:34 +00:00
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__init__.py	compat.fhdl.bitcontainer: import/wrap Migen code.	2018-12-12 15:22:34 +00:00
bitcontainer.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
conv_output.py	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00
module.py	compat.fhdl.module: fix finalization of transformed compat submodules.	2019-08-08 07:45:34 +00:00
specials.py	compat.fhdl.specials: track changes in build.plat.	2019-08-03 22:52:34 +00:00
structure.py	compat.fhdl.structure: fix If/Elif/Else after 32446831.	2019-07-03 13:19:15 +00:00
verilog.py	hdl.ir: call back from Fragment.prepare if a clock domain is missing.	2019-08-03 14:54:20 +00:00