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Author SHA1 Message Date
whitequark 5c626e33bf compat.fhdl.module: fix finalization of transformed compat submodules. 
Before this commit, the TransformedElaboratable of a CompatModule
would be ignored, and .get_fragment() would be used to retrieve
the CompatModule within.

After this commit, the finalization process is reworked to match
oMigen's finalization closely, and all submodules, native and compat,
are added in the same way that preserves applied transforms.
 2019-08-08 07:45:34 +00:00
whitequark 0fe05188e8 compat.fhdl.specials: track changes in build.plat. 2019-08-03 22:52:34 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark 668ff40a75 compat.fhdl.specials: mark CompatMemory as Elaboratable. 
This suppresses a warning that is not useful in the compat context.
 2019-07-03 13:28:57 +00:00
whitequark eeb6aca93d compat.fhdl.specials: use "sync" as default domain, not "sys". 
In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
 2019-07-03 13:25:12 +00:00
whitequark c98b8f7c07 compat.fhdl.specials: fix Memory.get_port() after 94e8f479. 
This also makes sure the native ports are instantiated for correct
clock domain.
 2019-07-03 13:24:00 +00:00
whitequark 9eb81609d6 compat.fhdl.structure: fix If/Elif/Else after 32446831. 2019-07-03 13:19:15 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark 2f7e52369c compat.fhdl.structure: fix typo. 2019-06-25 22:01:14 +00:00
whitequark b1af0601fa compat.fhdl.structure: simplify handling of default case. 2019-06-25 22:01:14 +00:00
whitequark 2566747061 compat.fhdl.structure: fix Case().makedefault(). 
Fixes #100.
 2019-06-13 03:56:57 +00:00
whitequark f689b777b4 compat.fhdl.structure: always order default case as the very last. 2019-06-13 03:56:57 +00:00
whitequark 537d91851d compat.fhdl.module: silence "unused elaboratable" warnings. 2019-06-04 13:09:36 +00:00
whitequark 38917e4523 compat.fhdl.specials: fix platform lowering for TSTriple again. 2019-06-04 13:03:56 +00:00
whitequark 79a3710255 compat.fhdl.specials: fix platform lowering. 
get_tristate only has O/OE; the triple is created by get_input_output.
 2019-06-04 12:26:09 +00:00
whitequark 0cbb743df9 compat.fhdl.module: implement some TODO'd deprecation warnings. 2019-06-04 12:00:02 +00:00
whitequark 39ca0e6fa6 compat.fhdl.module: CompatModule should be elaboratable. 
Fixes #83.
 2019-06-04 11:11:31 +00:00
whitequark 4c443a7ef5 compat.fhdl.specials: TSTriple is not an elaboratable. 2019-06-03 09:39:38 +00:00
Chris Osterwood 699fe5a675 Add import so that Tristate.elaborate builds 2019-05-20 16:34:31 +00:00
Alain Péteut c8e92c0612 compat.fhdl.specials: fix Tristate, TSTriple. 
* fix TSTriple instance.
* TSTriple, Tristate: tag as Elaboratable
 2019-04-22 09:57:12 +00:00
Alain Péteut 371dc8bebe compat.fhdl.specials: fix Tristate. 2019-04-22 08:49:08 +00:00
whitequark 93d15abcf1 compat.fhdl.specials: fix TSTriple. 2019-04-22 08:15:03 +00:00
whitequark 287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
whitequark e844b0e095 compat.fhdl.module: fix typo. 2019-01-26 23:08:55 +00:00
whitequark ce7ba70462 compat.fhdl.specials: fix __all__ list. 2019-01-26 22:59:33 +00:00
whitequark 7890c0adc8 test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark e3b5b2acc8 fhdl.specials: add compatibility shim for Tristate. 2019-01-19 02:20:40 +00:00
whitequark 5361b4c22b compat: fix confusing naming for memory port address signal. 2018-12-22 00:53:05 +00:00
whitequark 0df543b204 compat: do not finalize native submodules twice. 2018-12-22 00:02:31 +00:00
whitequark 00ef7a78d3 compat: provide verilog.convert shim. 2018-12-21 13:53:06 +00:00
whitequark 568d3c5b7d compat: provide Memory shim. 2018-12-21 13:15:52 +00:00
whitequark a90748303c compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices. 2018-12-18 20:03:32 +00:00
whitequark 015998eba9 hdl.dsl: add clock domain support. 2018-12-16 23:51:24 +00:00
whitequark db5fd1e4c4 compat.fhdl.structure: only convert to bool in If/Elif if necessary. 2018-12-16 17:41:42 +00:00
whitequark 286a8009c8 compat.fhdl: reexport Array. 2018-12-16 10:39:54 +00:00
whitequark 790eb05a92 Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
whitequark 9010805040 compat.fhdl.structure: handle If/Elif with multi-bit condition. 2018-12-15 00:10:54 +00:00
whitequark ecea721f43 compat.fhdl.module: allow adding native submodules to compat modules. 2018-12-14 23:56:50 +00:00
whitequark 1c7b43ea49 Fix deprecations in Python 3.7. 2018-12-14 23:56:50 +00:00
whitequark 3bc3647380 compat.fhdl.module: fix specials. 2018-12-14 16:14:08 +00:00
whitequark 3b23645fb7 compat: add fhdl.specials.TSTriple shim. 2018-12-14 16:09:51 +00:00
whitequark baba47251c compat.fhdl.module: update deprecation messages. 2018-12-14 16:01:38 +00:00
whitequark 6251c95d4e compat.genlib.fsm: import/wrap Migen code. 2018-12-13 12:41:19 +00:00
whitequark f4340c19bb fhdl: cd_name→domain. 2018-12-13 10:15:01 +00:00
whitequark 22c76e5f90 compat.fhdl.module: implement finalization. 2018-12-13 02:36:15 +00:00
whitequark f0f4c0ce61 fhdl.ast: bits_sign→shape. 2018-12-13 02:06:58 +00:00
whitequark b4dab74b2e compat.fhdl.{module,structure}: import/wrap Migen code (WIP). 2018-12-12 15:47:34 +00:00
whitequark 356852a570 compat.fhdl.bitcontainer: import/wrap Migen code. 2018-12-12 15:22:34 +00:00