whitequark 6bfff25e76 vendor: yosys is not a required tool for proprietary toolchains. ... Since commit b9799b4c, the discovery mechanism for the Yosys required to produce Verilog is different from the usual require_tool(); namely it is possible to produce Verilog without a `yosys` binary on PATH. Fixes #419.		2020-07-02 18:13:54 +00:00
..
back	back.pysim: simplify.	2020-06-28 05:04:16 +00:00
build	vendor.intel: double-quote Tcl values rather than brace-quoting.	2020-05-21 09:48:42 +00:00
compat	Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation	2020-04-02 02:46:44 +00:00
hdl	Add (heavily work in progress) documentation.	2020-06-30 22:21:16 +00:00
lib	lib.cdc: update PulseSynchronizer to follow conventions.	2020-06-28 05:17:33 +00:00
test	Add (heavily work in progress) documentation.	2020-06-30 22:21:16 +00:00
vendor	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
__init__.py	Gracefully handle missing dependencies.	2020-07-01 07:00:02 +00:00
_toolchain.py	Refactor build script toolchain lookups.	2019-10-13 13:53:24 +00:00
_unused.py	_unused: extract must-use logic from hdl.ir.	2020-02-01 01:35:05 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
_yosys.py	Gracefully handle missing dependencies.	2020-07-01 07:00:02 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	back.cxxrtl: new backend.	2020-06-11 16:19:40 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix get_var_name() to work on toplevel attributes.	2020-05-17 19:51:58 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00