whitequark 23da2fdda6 vendor.xilinx_{7series,ultrascale}: remove grade property. ... This was added in commit bfd4538d based on a misunderstanding of how Xilinx part numbers work. * non-ultrascale 7-series parts don't have temperature grades; * ultrascale parts have temperature grade as a part of speed grade.		2020-07-08 09:08:00 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	vendor.intel: don't use write_verilog -decimal.	2020-05-21 09:49:42 +00:00
lattice_ecp5.py	vendor.lattice_ecp5: Add support for io with xdr=7	2020-07-06 16:12:07 +00:00
lattice_ice40.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
lattice_machxo2.py	vendor.lattice_machxo2: add back as a compatibility shim.	2020-06-21 17:28:01 +00:00
lattice_machxo_2_3l.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
xilinx_7series.py	vendor.xilinx_{7series,ultrascale}: remove grade property.	2020-07-08 09:08:00 +00:00
xilinx_spartan_3_6.py	vendor: yosys is not a required tool for proprietary toolchains.	2020-07-02 18:13:54 +00:00
xilinx_ultrascale.py	vendor.xilinx_{7series,ultrascale}: remove grade property.	2020-07-08 09:08:00 +00:00