whitequark 91ef2f58e3 vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals. ... Fixes #88.		2019-09-20 16:26:27 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
lattice_ecp5.py	vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.	2019-09-20 16:26:27 +00:00
lattice_ice40.py	vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.	2019-09-20 16:26:27 +00:00
xilinx_7series.py	vendor.xilinx_{7series,spartan3_6}: specialize MultiReg.	2019-09-20 15:13:27 +00:00
xilinx_spartan_3_6.py	vendor.xilinx_{7series,spartan3_6}: specialize MultiReg.	2019-09-20 15:13:27 +00:00