whitequark c75fa45fd8 vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter. ... The parameter defaults to "ULTRASCALE", even when synthesizing for 7-series devices. This could lead to a simulation/synthesis mismatch, and causes a warning. Fixes #438.		2020-07-23 16:38:28 +00:00
..
_toolchain	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00
back	back.rtlil: lower maximum accepted wire size.	2020-07-22 14:43:44 +00:00
build	vendor.intel: double-quote Tcl values rather than brace-quoting.	2020-05-21 09:48:42 +00:00
compat	compat.fhdl.bitcontainer: fix value_bits_sign().	2020-07-21 02:53:29 +00:00
hdl	hdl.ast: don't inherit Shape from NamedTuple.	2020-07-07 05:17:03 +00:00
lib	lib.cdc: fix typo.	2020-07-13 23:53:15 +00:00
sim	sim._pycoro: avoid spurious wakeups.	2020-07-22 14:32:45 +00:00
test	hdl.ast: don't inherit Shape from NamedTuple.	2020-07-07 05:17:03 +00:00
vendor	vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter.	2020-07-23 16:38:28 +00:00
__init__.py	Gracefully handle missing dependencies.	2020-07-01 07:00:02 +00:00
_unused.py	_unused: extract must-use logic from hdl.ir.	2020-02-01 01:35:05 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	back.cxxrtl: new backend.	2020-06-11 16:19:40 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix get_var_name() to work on toplevel attributes.	2020-05-17 19:51:58 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00