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compat
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Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation
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2020-04-02 02:46:44 +00:00 |
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__init__.py
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test: use #nmigen: magic comment instead of monkey patch.
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2019-10-26 06:37:08 +00:00 |
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test_build_dsl.py
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build.dsl: allow strings to be used as connector numbers.
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2020-01-31 03:11:34 +00:00 |
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test_build_plat.py
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build.plat: in Platform.add_file(), allow adding exact duplicates.
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2019-11-15 23:40:44 +00:00 |
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test_build_res.py
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test_build_res: fix after commit 3e2ecdf2.
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2020-02-07 00:07:19 +00:00 |
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test_compat.py
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{,_}tools→{,_}utils
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2019-10-13 18:53:38 +00:00 |
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test_examples.py
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test: fix example test after commit a7b8ced9.
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2020-06-11 16:36:08 +00:00 |
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test_hdl_ast.py
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hdl.ast: don't inherit Shape from NamedTuple.
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2020-07-07 05:17:03 +00:00 |
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test_hdl_cd.py
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{,_}tools→{,_}utils
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2019-10-13 18:53:38 +00:00 |
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test_hdl_dsl.py
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Add (heavily work in progress) documentation.
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2020-06-30 22:21:16 +00:00 |
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test_hdl_ir.py
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hdl.ir: typecheck convert(ports=) more carefully.
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2020-04-24 21:15:00 +00:00 |
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test_hdl_mem.py
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hdl.mem: add synthesis attribute support.
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2020-02-06 14:53:16 +00:00 |
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test_hdl_rec.py
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hdl.rec: preserve shapes when constructing a layout.
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2020-06-05 03:19:46 +00:00 |
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test_hdl_xfrm.py
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hdl.xfrm: preserve allow_reset_less when transforming ResetSignal.
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2020-06-06 11:43:25 +00:00 |
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test_lib_cdc.py
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lib.cdc: update PulseSynchronizer to follow conventions.
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2020-06-28 05:17:33 +00:00 |
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test_lib_coding.py
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back.pysim: redesign the simulator.
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2019-11-28 21:05:34 +00:00 |
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test_lib_fifo.py
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Correctly handle resets in AsyncFIFO.
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2020-03-14 23:26:07 +00:00 |
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test_lib_io.py
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hdl.rec: preserve shapes when constructing a layout.
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2020-06-05 03:19:46 +00:00 |
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test_sim.py
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back.pysim: synchronize waveform writing with cxxrtl.
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2020-07-07 04:09:02 +00:00 |
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utils.py
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test: remove FHDLTestCase.assertRaisesRegex.
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2020-07-02 22:50:20 +00:00 |
