whitequark f8428ff505 back.rtlil: infer bit width for instance parameters. ... Otherwise, Yosys assumes it is always 32, which is often inappropriate.		2019-11-27 17:58:42 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00
rtlil.py	back.rtlil: infer bit width for instance parameters.	2019-11-27 17:58:42 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00