whitequark f8428ff505 back.rtlil: infer bit width for instance parameters. ... Otherwise, Yosys assumes it is always 32, which is often inappropriate.		2019-11-27 17:58:42 +00:00
..
back	back.rtlil: infer bit width for instance parameters.	2019-11-27 17:58:42 +00:00
build	build.plat: in Platform.add_file(), allow adding exact duplicates.	2019-11-15 23:40:44 +00:00
compat	compat.fhdl.specials: fix argument parsing compatibility.	2019-10-17 07:54:36 +00:00
hdl	hdl.ir: for instance ports, prioritize defs over uses.	2019-11-26 21:19:03 +00:00
lib	lib.io: use keyword-only arguments in Pin().	2019-10-16 19:50:04 +00:00
test	hdl.ir: for instance ports, prioritize defs over uses.	2019-11-26 21:19:03 +00:00
vendor	vendor.xilinx_*: Set IOB attribute on cels instead of nets.	2019-11-18 15:04:03 +00:00
__init__.py	Explicitly restrict prelude imports.	2019-10-21 10:39:21 +00:00
_toolchain.py	Refactor build script toolchain lookups.	2019-10-13 13:53:24 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00