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Author SHA1 Message Date
Catherine
4014aef033 docs: change mobile navbar color too. 2024-01-05 12:28:22 +00:00
Piotr Esden-Tempski
7eea9c39cf docs: fix nav-bar on mobile 
The side nav-bar tweaks should only be valid when the side nav bar is present. It is only present on displays wider than 769px.
 2024-01-04 20:14:07 +00:00
Catherine
996fcfbda4 docs: match sidebar background color to logo. 2024-01-04 16:47:32 +00:00
Catherine
8ac22bc114 docs: add logo. 2024-01-04 16:47:32 +00:00
Catherine
0191011bde docs: links should be underlined. 2024-01-04 16:47:32 +00:00
Catherine
e356ee2cac docs: strip .editable suffix from version. 
This shows up in CI builds as well, since those use `pip install -e`.
 2024-01-04 16:47:32 +00:00
Jaro Habiger
c00e770f01 build.run: deprecate run_script argument in BuildPlan.execute_local() 2024-01-03 14:08:34 +00:00
Jaro Habiger
b823a8ee9d build.run: add BuildPlan.execute_docker() 
One usecase for this is using amaranth with vivado on macOs.
 2024-01-03 14:08:34 +00:00
Jaro Habiger
3200a3961d build.run: factor out extract method 2024-01-03 14:08:34 +00:00
Jaro Habiger
cc9fe89049 hdl.ast: fix Array not being indexable by ValueCastable 2024-01-03 13:46:16 +00:00
Catherine
5d9ad62f36 build.plat,vendor: start build.sh with #!/bin/sh. 
The build scripts generated by Amaranth are designed to be invoked by
directly running them with any shell (some of them will re-invoke
themselves with `bash` specifically, when it's a toolchain requirement),
and they're not currently marked executable, so there's no shebang.

Add a shebang line to improve compatibility with cases where they are
treated as executables in their own right.
 2024-01-03 11:45:57 +00:00
Wanda
0849e1af0b hdl.ast: make Slice const-castable. 
Fixes #1006.
 2023-12-30 11:28:03 +00:00
Wanda
6780c838b2 hdl.ast: fix Const.cast(Cat(...)) handling for signed numbers. 2023-12-30 11:27:08 +00:00
Catherine
82d35fb932 docs/lang: document clock domains. 2023-12-19 01:54:46 +00:00
Catherine
8dec39d37f docs/lang: expand to include all control flow syntax. 2023-12-19 01:54:46 +00:00
Wanda
8cd8cdde2b Implement RFC 20: Remove non-FWFT FIFOs. 
Fixes #875.
 2023-12-13 11:41:19 +00:00
Catherine
3ed78d98ea Implement RFC 18: Reorganize vendor platforms 
Closes #873.
 2023-12-13 11:24:37 +00:00
Catherine
9d4ffab104 compat: remove. 
Fixes #692.
 2023-12-13 11:20:12 +00:00
Catherine
750cbbc3c7 hdl: remove deprecated Sample, Past, Stable, Rose, Fell. 2023-12-13 11:13:14 +00:00
Catherine
475b0f35dd Implement RFC 19: Remove amaranth.lib.scheduler. 
Closes #874.
 2023-12-13 09:53:54 +00:00
Catherine
597b1b8839 Implement RFC 5: Remove Const.normalize. 
Closes #754.
 2023-12-13 09:53:54 +00:00
Catherine
a2f3c544ee Release version 0.4. 2023-12-13 09:29:50 +00:00
Catherine
73e3ee695d docs/changes: add some missing items. 2023-12-13 09:29:50 +00:00
Catherine
fc4d70486a docs/stdlib: write an introductory section. 
Co-authored-by: Wanda <wanda-phi@users.noreply.github.com>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2023-12-11 22:57:30 +00:00
Catherine
a2aa07cbc7 lib.wiring: document amaranth-lang/rfcs#2. WIP 
Co-authored-by: Charlotte <charlotte@hrzn.ee>
 2023-12-11 22:57:30 +00:00
Jean-François Nguyen
d154bddf17 lib.wiring: preserve insertion order in SignatureMembers.__iter__. 2023-12-11 22:34:57 +00:00
Wanda
8e6ae9e6e0 Implement RFC 38: Component signature immutability. 
Fixes #996.
 2023-12-11 19:51:32 +00:00
Wanda
6ad0d21cc9 Implement RFC 37: Make `Signature` immutable. 
Fixes #995.
 2023-12-11 19:01:32 +00:00
Catherine
b9c2404f22 lib.wiring: make values of In and Out be strings "In" and "Out". 
Their `str()` and `repr()` values are already that; and the 0 and 1
don't make sense. The RFC leaves it unspecified.
 2023-12-11 18:04:37 +00:00
Wanda
3d0c5426df docs: Add changelog entries for RFCs 34, 35. 2023-12-11 10:39:02 +00:00
Wanda
e9545efb22 Implement RFC 35: Add ShapeLike, ValueLike. 2023-12-09 13:57:30 +00:00
Wanda
422ba9ea51 lib.wiring: use tracer to obtain default Signature path and src_loc. 
Fixes #987.
 2023-12-07 21:50:34 +00:00
Catherine
7db049f37f Remove remaining traces of $verilog_initial_trigger. 
This construct was originally removed in commit b452e0e8. It has not been relevant since Yosys 0.10.
 2023-12-07 21:10:11 +00:00
Catherine
120375dabe lib.wiring: fix __repr__ for PureInterface subclasses. 
Fixes #988.
 2023-12-05 04:46:11 +00:00
Wanda
0cdcab0fbb Implement RFC 34: Rename amaranth.lib.wiring.Interface to PureInterface. 2023-12-04 21:41:47 +00:00
Wanda
ab6503e352 lib.wiring: add __repr__ to Interface. 2023-12-03 02:00:20 +00:00
Wanda
28139f5f4b sim: disambiguate duplicate names of traced signals 
Fixes #976.
 2023-12-03 00:51:35 +00:00
Catherine
193fdaccd0 lib.data: mark Field as @final. 2023-12-01 20:50:35 +00:00
Catherine
3597c48eee lib.data: improve FlexibleLayout documentation. 
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2023-12-01 20:50:35 +00:00
Wanda
ef5cfa72bc Implement RFC 31: Enumeration type safety. 2023-11-29 10:50:34 +00:00
Catherine
b0b193f1ad sim.pysim: admit non-signals in write_vcd(traces=...). 
Rather than requiring each additional requested trace to be a signal,
all of the signals in the provided value are added to the GTKW file and
to the VCD file if they are not already there. This improves usability
for `lib.data` as struct fields can now be added to traces.
 2023-11-28 12:21:21 +00:00
Wanda
c6000b1097 lib.data: implement equality for View, reject all other operators. 2023-11-27 21:44:52 +00:00
Catherine
4bfe2cde6f sim: add support for dumping structure fields in VCD. 
See #790.

This commit adds an entirely private API for describing formatting of
values that is used in the standard library, in departure from our
standing policy of not using private APIs in the standard library.

This is a temporary measure intended to get the version 0.4 released
faster, as it has been years in the making. It is expected that this
API will be made public in the version 0.5 after going through the usual
RFC process.

This commit only adds VCD lines for fields defined in `lib.data.Layout`
when using `sim.pysim`. The emitted RTLIL and Verilog remain the same.
It is expected that when `sim.cxxsim` lands, RTLIL/Verilog output will
include aliases for layout fields as well.

The value representation API also handles formatting of enumerations,
with no changes visible to the designer. The implementation of
`Signal(decoder=)` is changed as well to use the new API, with full
backwards compatibility and no public API changes.

Co-authored-by: Wanda <wanda@phinode.net>
 2023-11-27 19:03:13 +00:00
Catherine
04f906965a lib.wiring: in is_compliant(sig, obj), check that obj is an interface object with that signature. 
Fixes #935.
 2023-11-27 18:50:41 +00:00
Catherine
8b48af6de8 lib.wiring: make sig.members += actually work. 2023-11-27 15:42:24 +00:00
Catherine
02756f6ec7 lib.wiring: comment cleanup. NFC 2023-11-27 15:42:24 +00:00
Catherine
1eea38c9c0 docs: fix sidebar CSS. 2023-11-27 15:42:24 +00:00
Catherine
b2d8a18cbf lib.wiring: fix _gettypeattr fallback path. 2023-11-27 15:42:24 +00:00
Catherine
a2e87b370e lib.wiring: fix typo in Signature.flatten. 2023-11-27 15:42:24 +00:00
Wanda
57748a66a6 lib.io: fix Pin.eq to work when FlippedInterface is involved. 
This was broken by #915, when platform started handing out
`FlippedInterface` versions of `Pin`.
 2023-11-27 06:35:55 +00:00