whitequark
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1b7f8c7950
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back.pysim: general clean-up.
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2018-12-14 12:22:03 +00:00 |
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whitequark
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105113f1d8
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back.pysim: accept any valid assignments from processes.
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2018-12-14 12:18:41 +00:00 |
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whitequark
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240a40c2c2
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back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
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2018-12-14 10:57:13 +00:00 |
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whitequark
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7d91dd56c8
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fhdl.xfrm: implement DomainLowerer.
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2018-12-14 10:56:53 +00:00 |
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whitequark
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b34c1a9ad0
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back.pysim: undriven comb signals should return to reset value.
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2018-12-14 09:12:38 +00:00 |
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whitequark
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b58715c5dc
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ast, back.pysim: allow specifying user-defined decoders for signals.
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2018-12-14 09:02:29 +00:00 |
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whitequark
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bb843cb40c
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back.pysim: fix completely broken codegen for Switch.
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2018-12-14 08:51:36 +00:00 |
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whitequark
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6aefd0c04c
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back.pysim: raise an exception if delta cycles blow a process deadline.
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2018-12-14 08:10:21 +00:00 |
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whitequark
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a10791e160
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back.pysim: if requested, write a gtkw file with a useful preset.
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2018-12-14 08:04:29 +00:00 |
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whitequark
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cb998d891b
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back.pysim: explain how delta cycles work.
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2018-12-14 07:26:26 +00:00 |
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whitequark
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e4d08d2855
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back.pysim: delay clock processes by one half period.
Makes it easier to see initial delta cycles.
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2018-12-14 05:17:43 +00:00 |
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whitequark
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3bb7a87e0f
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back.pysim: implement "sync processes", like migen.sim generators.
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2018-12-14 05:13:58 +00:00 |
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whitequark
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d791b77cc8
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back.pysim: allow suspending processes until a tick in a domain.
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2018-12-14 04:33:06 +00:00 |
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whitequark
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3e59d857e1
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back.pysim: use bare ints for signal values (-5% runtime).
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2018-12-14 03:05:57 +00:00 |
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whitequark
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55e729f68a
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setup: add missing import.
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2018-12-14 02:32:37 +00:00 |
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whitequark
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b09f4b10ee
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back.pysim: collect handlers before running (-5% runtime).
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2018-12-13 18:34:44 +00:00 |
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whitequark
|
a7ebc02bdd
|
back.pysim: allow multiple registered handlers per signal.
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2018-12-13 18:28:11 +00:00 |
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whitequark
|
6a4004ef8d
|
back.pysim: fix handling of process termination.
|
2018-12-13 18:17:58 +00:00 |
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whitequark
|
fb27c2520b
|
back.pysim: new simulator backend (WIP).
|
2018-12-13 18:02:46 +00:00 |
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whitequark
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71f1f717c4
|
fhdl.cd: rename ClockDomain signals together with domain.
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2018-12-13 15:24:55 +00:00 |
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whitequark
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07c818e077
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fhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 14:34:07 +00:00 |
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whitequark
|
ac498414ab
|
back.verilog: remove debug code.
|
2018-12-13 13:42:54 +00:00 |
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whitequark
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90f1503c91
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fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
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2018-12-13 13:12:31 +00:00 |
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whitequark
|
6251c95d4e
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compat.genlib.fsm: import/wrap Migen code.
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2018-12-13 12:41:19 +00:00 |
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whitequark
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9661e897e6
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fhdl.ir: a subfragment's input that we don't drive is also our input.
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2018-12-13 11:50:56 +00:00 |
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whitequark
|
bb04c9e0da
|
fhdl, back: trace and emit source locations of values.
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2018-12-13 11:44:06 +00:00 |
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whitequark
|
859c2dbcf0
|
back.rtlil: never give subfragment cells names starting with $.
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2018-12-13 11:30:16 +00:00 |
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whitequark
|
b150f1915d
|
fhdl.ir: don't crash propagataing ports in empty fragments.
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2018-12-13 11:25:49 +00:00 |
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whitequark
|
72257b6935
|
fhdl.ir: implement clock domain propagation.
|
2018-12-13 11:01:03 +00:00 |
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whitequark
|
fde2471963
|
fhdl.ir: remove iter_domains().
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2018-12-13 10:18:57 +00:00 |
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whitequark
|
f4340c19bb
|
fhdl: cd_name→domain.
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2018-12-13 10:15:01 +00:00 |
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whitequark
|
c5087edfa5
|
fhdl.cd: add tests.
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2018-12-13 09:19:16 +00:00 |
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whitequark
|
9bee90f1bd
|
fhdl.xfrm: implement DomainRenamer.
|
2018-12-13 08:57:14 +00:00 |
|
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whitequark
|
8963ab5d9f
|
fhdl.xfrm: add test for ControlInserter with subfragments.
|
2018-12-13 08:45:10 +00:00 |
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whitequark
|
19aa404628
|
fhdl.xfrm: add tests for ResetInserter, CEInserter.
|
2018-12-13 08:39:02 +00:00 |
|
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whitequark
|
b1a89ef5fd
|
fhdl.ir: add tests for port propagation.
|
2018-12-13 08:09:39 +00:00 |
|
|
whitequark
|
c60392595b
|
Set up Travis CI.
|
2018-12-13 07:54:02 +00:00 |
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whitequark
|
1f1aa7f468
|
Add LICENSE.
|
2018-12-13 07:51:49 +00:00 |
|
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whitequark
|
48330f8742
|
setup: check Python version.
|
2018-12-13 07:47:07 +00:00 |
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whitequark
|
a797e27573
|
fhdl.dsl: add tests for lowering. 99% branch coverage.
|
2018-12-13 07:33:59 +00:00 |
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whitequark
|
d2e2d00e45
|
fhdl.cd: rename ClockDomain.{reset→rst}.
|
2018-12-13 07:27:27 +00:00 |
|
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whitequark
|
e0a81edf4d
|
fhdl.dsl: add tests for submodules.
|
2018-12-13 07:24:28 +00:00 |
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whitequark
|
932f1912a2
|
fhdl.dsl: use less error-prone Switch/Case two-level syntax.
|
2018-12-13 07:11:06 +00:00 |
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whitequark
|
f70ae3bac5
|
fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
|
2018-12-13 06:06:51 +00:00 |
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whitequark
|
5b8708017e
|
fhdl.ast: fix Switch._?hs_signals() for switch without statements.
|
2018-12-13 05:00:44 +00:00 |
|
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whitequark
|
4e32f6b8de
|
back.verilog: detect undriven public wires using Yosys.
This should never happen, and is certainly a logic bug in nMigen.
|
2018-12-13 04:59:48 +00:00 |
|
|
whitequark
|
27d3dfc453
|
back.rtlil: fix swapped operands in sync assign.
|
2018-12-13 04:34:22 +00:00 |
|
|
whitequark
|
6c7f98e964
|
back.rtlil: explain logic for CD reset insertion.
|
2018-12-13 03:51:00 +00:00 |
|
|
whitequark
|
2c67a620ee
|
back.rtlil: explicitly set the top module.
|
2018-12-13 03:50:04 +00:00 |
|
|
whitequark
|
4df5c5de65
|
fhdl.ir: explain how port enumeration works.
|
2018-12-13 03:31:13 +00:00 |
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