whitequark
33f32a25f5
back.rtlil: prepare for Yosys sigspec slicing improvements.
...
See YosysHQ/yosys#741 .
2018-12-16 18:03:14 +00:00
whitequark
9bce35098f
back.rtlil: avoid illegal slices.
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Not sure what to do with {} [] on LHS yet--fix Yosys?
2018-12-16 17:41:11 +00:00
whitequark
e86104d3a6
back.rtlil: use slicing to match shape when reducing width.
2018-12-16 16:20:45 +00:00
whitequark
2833b36c73
back.rtlil: don't emit a slice if all bits are used.
2018-12-16 16:05:38 +00:00
whitequark
9794e732e2
back.rtlil: reorganize value compiler into LHS/RHS.
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This also implements Cat on LHS.
2018-12-16 13:33:34 +00:00
whitequark
ed39748889
back.rtlil: fix naming. NFC.
2018-12-16 11:26:31 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
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This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
07c818e077
fhdl.ir: move Fragment prepare logic from back.rtlil.
2018-12-13 14:34:07 +00:00
whitequark
90f1503c91
fhdl.ir: record port direction explicitly.
...
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
2018-12-13 13:12:31 +00:00
whitequark
bb04c9e0da
fhdl, back: trace and emit source locations of values.
2018-12-13 11:44:06 +00:00
whitequark
859c2dbcf0
back.rtlil: never give subfragment cells names starting with $.
2018-12-13 11:30:16 +00:00
whitequark
72257b6935
fhdl.ir: implement clock domain propagation.
2018-12-13 11:01:03 +00:00
whitequark
fde2471963
fhdl.ir: remove iter_domains().
2018-12-13 10:18:57 +00:00
whitequark
f4340c19bb
fhdl: cd_name→domain.
2018-12-13 10:15:01 +00:00
whitequark
d2e2d00e45
fhdl.cd: rename ClockDomain.{reset→rst}.
2018-12-13 07:27:27 +00:00
whitequark
27d3dfc453
back.rtlil: fix swapped operands in sync assign.
2018-12-13 04:34:22 +00:00
whitequark
6c7f98e964
back.rtlil: explain logic for CD reset insertion.
2018-12-13 03:51:00 +00:00
whitequark
2c67a620ee
back.rtlil: explicitly set the top module.
2018-12-13 03:50:04 +00:00
whitequark
4df5c5de65
fhdl.ir: explain how port enumeration works.
2018-12-13 03:31:13 +00:00
whitequark
f86ec1e7ef
back.rtlil: explain how RTLIL conversion works.
2018-12-13 03:22:01 +00:00
whitequark
a17a9e355d
back.rtlil: give clocks and resets nicer names.
2018-12-13 02:43:02 +00:00
whitequark
b42620e490
back.rtlil: match shape of $mux ports A/B/Y.
2018-12-13 02:35:46 +00:00
whitequark
f0f4c0ce61
fhdl.ast: bits_sign→shape.
2018-12-13 02:06:58 +00:00
whitequark
0fac1f8d0f
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
2018-12-12 12:38:24 +00:00
whitequark
aab01d9e59
fhdl.ast.Signal: implement attrs field.
2018-12-12 11:30:40 +00:00
whitequark
851ed06769
ClockDomain.{rst→reset}, for consistency with ResetInserter.
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nmigen.compat.ClockDomain would alias this, for Migen compatibility.
2018-12-12 09:49:02 +00:00
whitequark
4d3258013d
Initial commit.
2018-12-12 03:18:44 +00:00
