Commit graph

858 commits

Author SHA1 Message Date
Jacob Lifshay 58f1d4bcb6
sim.pysim: write the next, not curr signal value to the VCD file
This is a temporary fix for #429.
2020-07-13 02:10:01 +00:00
whitequark 0a90aa1b17 sim.pysim: use VCD aliases to reduce space and time overhead.
On Minerva SoC, this reduces VCD file size by about 35%, and reduces
runtime overhead of writing VCDs by 10% or less.
2020-07-11 12:26:34 +00:00
whitequark 30e2f91176 sim: simplify. NFC. 2020-07-08 17:31:53 +00:00
whitequark d7a87fef42 back.pysim→sim.pysim; split into more manageable parts.
This is necessary to add cxxrtl as an alternate simulation engine.
2020-07-08 12:49:38 +00:00
whitequark 23da2fdda6 vendor.xilinx_{7series,ultrascale}: remove grade property.
This was added in commit bfd4538d based on a misunderstanding of how
Xilinx part numbers work.
 * non-ultrascale 7-series parts don't have temperature grades;
 * ultrascale parts have temperature grade as a part of speed grade.
2020-07-08 09:08:00 +00:00
whitequark 6d417568ad back.pysim: only extract signal names if VCD is requested.
This commit also fixes an issue introduced in 2606ee33 that regressed
simulator startup time and bloated VCD files. (It's actually about
10% faster now than *before* the regression was introduced.)
2020-07-08 08:33:45 +00:00
whitequark 3c3cfd48fb back.pysim: reset timeline as well.
This is a bug that was introduced in 94faf497b.
2020-07-08 08:19:29 +00:00
whitequark 90e2a991f0 back.pysim: simplify. NFC. 2020-07-08 06:31:04 +00:00
whitequark 94faf497ba back.pysim: extract timeline handling to class _Timeline. NFC. 2020-07-08 06:31:04 +00:00
whitequark d3d210eaee back.pysim: extract simulator commands to sim._cmds. NFC. 2020-07-08 05:42:33 +00:00
whitequark e435a21715 back.pysim: simplify. NFC. 2020-07-08 03:55:09 +00:00
awygle 659b0e8189
hdl.ast: don't inherit Shape from NamedTuple.
Fixes #421.
2020-07-07 05:17:03 +00:00
whitequark cee43f0de1 back.pysim: simplify.
Compiled process names were never particularly useful (comments in
the source would make more sense for debugging), and coroutine
process names were actually source locations.
2020-07-07 04:29:13 +00:00
whitequark c9030eb3cd back.pysim: simplify. NFC. 2020-07-07 04:19:05 +00:00
whitequark db4529a178 back.pysim: simplify. NFC. 2020-07-07 04:09:10 +00:00
whitequark 2efeb05c63 back.pysim: synchronize waveform writing with cxxrtl. 2020-07-07 04:09:02 +00:00
whitequark e012e62ade back.pysim: synchronize terms with cxxrtl. NFC. 2020-07-07 03:38:39 +00:00
whitequark c9ac85a045 back.pysim: simplify. NFC. 2020-07-07 03:38:39 +00:00
whitequark 8f6eab0f6c back.pysim: simplify. NFC. 2020-07-07 03:38:39 +00:00
whitequark 23758e30bc Remove everything deprecated in nmigen 0.2. 2020-07-07 03:38:39 +00:00
Konrad Beckmann d4946b060a vendor.lattice_ecp5: Add support for io with xdr=7
This adds support for IOs with xdr=7 using the
IODDR71B and ODDR71B primitives.
2020-07-06 16:12:07 +00:00
Konrad Beckmann 981e674081 vendor.lattice_ecp5: Add support for io with xdr=4
This adds support for IOs with xdr=4 using the
IDDRX2F and ODDRX2F primitives.
2020-07-06 16:12:07 +00:00
whitequark fd5ee548b6 test: remove FHDLTestCase.assertRaisesRegex.
This method is only there because I misunderstood the documentation
of unittest.
2020-07-02 22:50:20 +00:00
whitequark 8dd28fecc6 compat.fhdl.specials: fix handling of tristate (i=None) pins.
Fixes #406.
2020-07-02 22:22:44 +00:00
whitequark 369bc3e307 _yosys→_toolchain.yosys 2020-07-02 18:26:08 +00:00
whitequark 6bfff25e76 vendor: yosys is not a required tool for proprietary toolchains.
Since commit b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.

Fixes #419.
2020-07-02 18:13:54 +00:00
whitequark 126f0be731 Gracefully handle missing dependencies.
Some people's workflows involve not using `pip`. This is not
a recommended way to use nMigen, but is prevalent enough for good
enough reason that we try to keep them working anyway.
2020-07-01 07:00:02 +00:00
whitequark 399b8f9863 Add (heavily work in progress) documentation.
To render correctly, the docs require:
 * pygments/pygments#1441
2020-06-30 22:21:16 +00:00
whitequark 8dacbbb2b2 Don't use pkg_resources.
This package is deprecated and introduces a massive amount of startup
latency. On my machine with 264 installed Python packages, it reduces
the time required to `import nmigen` from ~100ms to ~200ms.
2020-06-30 22:11:47 +00:00
whitequark 25ce260207 lib.cdc: update PulseSynchronizer to follow conventions.
Fixes #370.
2020-06-28 05:17:33 +00:00
whitequark 2606ee33ad back.pysim: simplify.
Remove _EvalContext, which was a level of indirection serving almost
no purpose. (The only case where it would be useful is repeatedly
resetting a simulation that, each time it is reset, would create new
signals to communicate with between coroutine processes. In that case
the signal states would not be persisted in _SimulatorState, but
would be removed with the _EvalContext that is recreated each time
the simulation is reset. But this could be solved with a weak map
instead.)

This regresses simulator startup time by 10-15% for unknown reasons
but is necessary to align pysim and future cxxsim.
2020-06-28 05:04:16 +00:00
Alan Green 303ea18cb6
_yosys: handle unparseable versions
Do not use yosys binaries with unparseable version numbers. This ensures
that nmigen always knows what version of yosys it is generating RTLIL
for.

The effect of this change is that if the version number of the system
yosys is unparsable, nmigen will attempt to fallback to the builtin
Yosys.

Fixes #409.
2020-06-23 12:12:02 +00:00
whitequark 706eb03e6b vendor.lattice_machxo2: add back as a compatibility shim. 2020-06-21 17:28:01 +00:00
Gwenhael Goavec-Merou 0aef5f4d48
vendor.lattice_machxo*: add MachXO3L support. 2020-06-21 17:24:47 +00:00
whitequark 868d49eccd back.verilog: refactor Yosys script generation. NFCI.
In commit 5f30bcbb, back.cxxsim gained a nicer way to generate
a script; this commit brings it to back.verilog too.
2020-06-14 09:38:32 +00:00
whitequark 5f30bcbb14 back.cxxrtl: allow injecting black boxes. 2020-06-14 09:25:54 +00:00
whitequark eddc397509 _yosys: add a way to retrieve Yosys data directory.
This is important for CXXRTL, since that's where its include files
are located.
2020-06-14 00:31:34 +00:00
whitequark 45c61969fc _yosys: fix typo in error message. 2020-06-14 00:03:36 +00:00
whitequark ca360917ba test: fix example test after commit a7b8ced9. 2020-06-11 16:36:08 +00:00
whitequark 545e49c2ca back.cxxrtl: new backend. 2020-06-11 16:19:40 +00:00
whitequark bddec3741e _yosys: translate Yosys warnings to Python warnings.
This isn't used yet (the only Yosys warning we can get is useless),
but will be handy for CXXRTL.
2020-06-11 16:12:52 +00:00
whitequark a7b8ced92c nmigen.cli: fix file type autodetection code. 2020-06-11 15:36:43 +00:00
whitequark 133d4f47d1 back.verilog: remove unused imports. NFC. 2020-06-11 15:17:49 +00:00
Adam Greig 02e30b53cc
hdl.xfrm: preserve allow_reset_less when transforming ResetSignal.
Fixes #400.
2020-06-06 11:43:25 +00:00
Shawn Anastasio 2f7c3bf443
hdl.rec: preserve shapes when constructing a layout.
Preserve the original user-provided shape, while still checking 
its validity. This allows Enum decoders to work when specifying
record fields with Enums.

Fixes #393.
2020-06-05 03:19:46 +00:00
whitequark afa4345903 vendor.lattice_ice40: reword confusing comment. NFC. 2020-05-31 10:21:45 +00:00
Robin Ole Heinemann 26a15b31f7 hdl.ast: fix typo 2020-05-24 16:56:15 +00:00
whitequark b9799b4c4a back.verilog: fall back to nmigen_yosys package.
The nmigen-yosys PyPI package provides a custom, minimal build of
Yosys that uses (at the moment) wasmtime-py to deliver a single
WASM binary that can run on many platforms, and eliminates the need
to build Yosys from source.

Not only does this lower barrier to entry for new nMigen developers,
but also decouples nMigen from Yosys' yearly release cycle, which
lets us use new features and drop workarounds for Yosys bugs earlier.

The source for the nmigen-yosys package is provided at:
  https://github.com/nmigen/nmigen-yosys
The package is built from upstream source and released automatically
with no manual steps.

Fixes #371.
2020-05-22 16:51:00 +00:00
whitequark 43b1ed1bf6 vendor.intel: don't use write_verilog -decimal.
See commit 702e41ba for details.
2020-05-21 09:49:42 +00:00
whitequark 7238e58224 vendor.intel: double-quote Tcl values rather than brace-quoting.
For unknown reasons, Quartus treats {foo} and "foo" in completely
different ways, which is not true for normal Tcl code; specifically,
it preserves the braces if they are used. Because of this, since
commit 6cee2804, the vendor.intel package was completely broken.
2020-05-21 09:48:42 +00:00