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Author SHA1 Message Date
Thomas Watson 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements 2021-05-11 02:41:32 +00:00
Adam Greig d824795c2c
vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts. 
Fixes #604.
 2021-04-12 09:48:20 +00:00
whitequark c84d4aff6e CI: fix sri-csl/formal-methods PPA series. 
GHA's Ubuntu has been upgraded to Focal.
 2021-03-19 00:02:02 +00:00
whitequark c30dcea24d hdl.ast: handle int subclasses as slice start/stop values. 
Fixes #601.
 2021-03-18 23:52:23 +00:00
dx-mon f7c2b9419f compat.genlib.roundrobin: fix missing imports 2021-02-04 11:02:27 +00:00
nickoe 746886ca8a
vendor.xilinx_7series: fix tool names for symbiflow. 
Prefix "tools" with symbiflow_ as is done for the QuickLogic Symbiflow
toolchain. Installing symbiflow gives me the tools with the preifx, so I
guess this is the correct way to move forward.
 2021-01-31 18:08:44 +00:00
Katherine Temkin 09de190bd1 vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 
This fixes a logic bug introduced in
6ce2b21e19.
 2021-01-26 09:44:22 +00:00
Adam Greig 6ce2b21e19
vendor.lattice_ecp5: replicate OE signal for each output bit. 
nextpnr can only pack OE FFs into IOLOGIC when there's one OFS1P3DX per
output, rather than one shared instance.
 2021-01-23 18:06:52 +00:00
whitequark a2da34a5bc README: add ChipEleven as a sponsor. 2021-01-23 03:27:31 +00:00
Joel Stanley 490fca5745 docs: Update up_counter to avoid deprecation warning 
nmigen/docs/_code/up_counter.py:44: DeprecationWarning: instead of nmigen.back.pysim.*, use nmigen.sim.*
  from nmigen.back.pysim import Simulator
 2021-01-17 12:56:30 +00:00
Adam Greig 3a4b61c16e
vendor.lattice_ecp5: remove outdated comment in ECP5 platform. 
Starting with nextpnr c6401413a, nextpnr does pack *FS1P3DX
into IOLOGIC cells.
 2021-01-14 11:34:03 +00:00
Robin Ole Heinemann 9af8201727 lib.fifo.AsyncFIFOBuffered: fix output register accounting 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann 2a7a3aef87 lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann d15705cf4f lib.fifo: use proper clock domains in AsyncFIFO tests 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann 76efe862fa lib.fifo.AsyncFIFOBuffered: use FFSynchronizer instead of AsyncFFsynchronizer 
AsyncFFsynchronizer only synchronizes one edge
 2021-01-06 01:05:46 +00:00
whitequark b466b724fe Revert "vendor.xilinx_7series: byte swap generated bitstream" 
This reverts commit 14a5c42a8b.
 2020-12-12 22:08:57 +00:00
whitequark 7dde2aac7c hdl.ast: formatting. NFC. 2020-12-12 15:42:23 +00:00
whitequark 818c8bc464 hdl.ast: normalize case values to two's complement, not signed binary. 
This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).

Fixes #559.
 2020-12-12 12:42:12 +00:00
whitequark 4e7e0b33d5 back.rtlil: give private items an appropriate name. NFCI. 2020-12-12 12:20:49 +00:00
whitequark 59ef6e6a1c build.plat: make verbose work like all other overrides. 
Fixes #497.
 2020-11-24 23:07:09 +00:00
whitequark 90e3504097 vendor.intel: implement add_settings (QSF) and add_constraints (SDC) overrides. 2020-11-24 20:35:58 +00:00
whitequark f1473e483a vendor.xilinx_spartan_3_6: fix typo. 
This was introduced in commit 2f8669ca.

Fixes #549.
 2020-11-22 00:16:02 +00:00
whitequark 39ff7203ba hdl.ast: remove dead code. NFC. 
See #548.
 2020-11-21 17:30:28 +00:00
awygle c1ed90807b
nmigen.hdl.rec: restore Record.shape(). 
This method was lost in commit abbebf8e.
 2020-11-17 19:36:58 +00:00
Marcelina Kościelnicka 44318149e0
sim._pyrtl: mask Mux selection operand. 
Otherwise it behaves funny when it's eg. the result of operator ~.
 2020-11-14 15:22:34 +00:00
Jan Kowalewski adef3b2e7b vendor.quicklogic: enable SoC clock configuration 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2020-11-13 16:27:15 +00:00
whitequark 36bc1d2b4d vendor.quicklogic: write OpenOCD scripts as part of build process. 
The OpenOCD scripts for EOS-S3 are roughly equivalent to SVF files
for a more traditional FPGA, which we also produce, for some common
"default" configuration, as a part of the build process.
 2020-11-13 05:44:16 +00:00
whitequark d6da4c257b build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files. 
This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.
 2020-11-10 05:30:30 +00:00
awygle ea94c9cc45
hdl.rec: proxy operators correctly. 
Commit abbebf8e used __getattr__ to proxy Value methods called on 
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.

Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.

Fixes #533.
 2020-11-09 20:20:25 +00:00
Konrad Beckmann ebbdac9798
vendor.intel: add support for Cyclone V internal oscillator 
When using the default clock "cyclonev_oscillator" on Cyclone V devices,
the internal oscillator will be used.
 2020-11-06 11:35:18 +00:00
whitequark bde37fe2f2 hdl.ast: deprecate UserValue in favor of ValueCastable. 
Closes #527.
 2020-11-06 02:21:53 +00:00
whitequark c9fd000103 sim.pysim: avoid redundant VCD updates. 
This commit properly addresses a bug introduced in 2efeb05c and then
temporarily fixed in 58f1d4bc.

Fixes #429.
 2020-11-06 02:05:35 +00:00
whitequark 6e7dbe004e examples: clean up oudated code. 2020-11-06 01:54:30 +00:00
whitequark bb6a233626 Fix commit 8313d6e7. 2020-11-06 01:54:30 +00:00
whitequark 8313d6e71c cli: update deprecated import. 2020-11-06 01:41:41 +00:00
whitequark db5a981f43 CI: add CPython 3.9 to test matrix. 2020-11-06 01:41:41 +00:00
whitequark 10fd5cff4b CI: run testsuite with -Werror. 2020-11-06 01:38:03 +00:00
whitequark c6150d0586 vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires. 
These only matter in simulation and after conversion to Verilog.
During synthesis they cause Yosys to produce warnings:

  Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.
 2020-11-06 01:31:14 +00:00
awygle abbebf8efe
hdl.rec: migrate Record from UserValue to ValueCastable. 
Closes #528.
 2020-11-06 01:10:39 +00:00
awygle 06c734992f
hdl.ast: implement ValueCastable. 
Closes RFC issue #355.
 2020-11-06 00:20:54 +00:00
whitequark 0ef01b1282 vendor.quicklogic: part→package 2020-11-05 07:36:43 +00:00
Norbert Braun 14a5c42a8b vendor.xilinx_7series: byte swap generated bitstream 
The Zynq driver in the FPGA Manager framework on Linux expects bitstreams that
are byte swapped with respect to what the Vivado command
`write_bitstream -bin_file` produces. Thus, use the `write_cfgmem` command with
appropriate options to generate the bitstream (.bin file).

Fixes #519.
 2020-11-03 09:39:49 +00:00
Jaro Habiger b15f0562a6 lib.fifo: fix {r,w}_level in AsyncFIFOBuffered 2020-11-03 09:34:12 +00:00
Jaro Habiger c7014f84ea lib.fifo: fix level on fifo full 2020-11-03 09:20:30 +00:00
David Lattimore 781a3aa767
vendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC instance. 
Fixes #520.
 2020-11-02 06:19:47 +00:00
Jan Kowalewski 8fe319f065 vendor.quicklogic: utilize internal SoC clock in EOS-S3 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2020-10-30 18:11:25 +00:00
Jan Kowalewski b88009bd96 vendor.quicklogic: fix toolchain nomenclature 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2020-10-30 18:11:25 +00:00
Robin Ole Heinemann 05decc43b2 lib.fifo.AsyncFFSynchronizer: check input and output signal width 2020-10-28 00:08:38 +00:00
Ben Newhouse 765c15c709
setup: link to latest docs if VCS information is not available. 2020-10-27 01:16:25 +00:00
whitequark e3207b74f4 build.dsl: clean up inversion logic. 
* Add invert= argument to DiffPairs() constructor, like in Pins().
  * Make PinsN() and DiffPairsN() pass invert= to the corresponding
    construtor instead of mutating.
 2020-10-26 19:50:21 +00:00