whitequark
9f643ce005
Clean up imports.
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This commit:
* moves lists of universally useful imports from `nmigen` to
`nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
* replaces lots of imports from individual parts of `nmigen.hdl`
with a star import from `nmigen.hdl`;
* replaces imports in tests with what we expect downstream code
to use;
* adds some missing imports in `nmigen.formal`.
2019-06-04 08:18:50 +00:00
whitequark
c89c2ce941
vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer.
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Fixes #82 .
2019-06-04 06:43:10 +00:00
whitequark
45d1dc1d54
vendor.board.tinyfpga_bx: fix typo.
2019-06-04 06:20:01 +00:00
whitequark
6426b90e4a
vendor.conn.pmod: implement.
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Fixes #79 .
2019-06-03 16:49:59 +00:00
whitequark
0fa45b5e14
vendor.board: extract package.
2019-06-03 16:14:59 +00:00
whitequark
2ca0834d41
vendor.tinyfpga_bx: add connectors.
2019-06-03 15:40:57 +00:00
whitequark
7c5461d210
vendor.icestick: add connectors.
2019-06-03 15:15:45 +00:00
whitequark
f351e2bd1e
vendor.ice40_hx1k_blink_evn: add (some) connectors.
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I have no idea how to lay out the Arduino-like connectors best,
so they're just missing.
2019-06-03 15:03:49 +00:00
whitequark
ed64880cc4
build.{plat,res}: add support for connectors.
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Fixes #77 .
2019-06-03 15:02:15 +00:00
whitequark
639e64c388
vendor.fpga.lattice_ice40: implement differential output buffers.
2019-06-03 09:28:27 +00:00
whitequark
41adcc3f97
vendor.fpga.lattice_ice40: implement differential input buffers.
2019-06-03 08:38:12 +00:00
whitequark
3116d4add2
vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras.
2019-06-03 07:54:28 +00:00
whitequark
185abb492d
vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers.
2019-06-03 07:43:31 +00:00
whitequark
6fae06aea9
build.{dsl,plat,res}: allow dir="oe".
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Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.
E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
2019-06-03 04:42:55 +00:00
whitequark
9ba2efd86b
build.{res,plat}: use xdr=0 as default, not xdr=1.
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The previous behavior was semantically incorrect.
2019-06-03 03:36:32 +00:00
whitequark
3327deae92
vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.
2019-06-03 03:01:56 +00:00
whitequark
dc17d06fe9
vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
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The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
2019-06-03 02:51:59 +00:00
whitequark
98497b2075
build.dsl: require a dict for extras instead of a stringly array.
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Fixes #72 .
2019-06-02 23:36:21 +00:00
whitequark
e4ebe03115
vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles.
2019-06-02 04:12:50 +00:00
whitequark
37152c733e
vendor.tinyfpga_{b→bx}
2019-06-02 04:11:28 +00:00
whitequark
bff08c5016
vendor.tinyfpga_b: fix IO_STANDARD.
2019-06-02 04:04:07 +00:00
Simon Kirkby
358b98e5de
vendor.tinyfpga_b: implement.
2019-06-02 01:20:09 +00:00
whitequark
39fad9a955
vendor.icestick: fix typo.
2019-06-02 01:13:03 +00:00
whitequark
ba0fcddb2c
vendor.ice40_hx1k_blink_evn: implement.
2019-06-01 16:48:07 +00:00
whitequark
eab372383a
vendor.icestick: implement.
2019-06-01 16:47:20 +00:00
whitequark
321d245e95
vendor.fpga.lattice_ice40: implement.
2019-06-01 16:47:01 +00:00
